📄 guangshanchi.tan.qmsg

📁 光栅尺的四细分和辩向电路
💻 QMSG
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "16 " "Warning: Found 16 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~152 " "Info: Detected gated clock \"CntOut:inst\|inst2~152\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~152" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~151 " "Info: Detected gated clock \"CntOut:inst\|inst2~151\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~151" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~150 " "Info: Detected gated clock \"CntOut:inst\|inst2~150\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~150" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "SubDir:inst1\|8~156 " "Info: Detected gated clock \"SubDir:inst1\|8~156\" as buffer" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 480 728 792 552 "8" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SubDir:inst1\|8~156" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~149 " "Info: Detected gated clock \"CntOut:inst\|inst2~149\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~149" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~148 " "Info: Detected gated clock \"CntOut:inst\|inst2~148\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~148" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~147 " "Info: Detected gated clock \"CntOut:inst\|inst2~147\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~147" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~54 " "Info: Detected gated clock \"CntOut:inst\|inst2~54\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~54" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~53 " "Info: Detected gated clock \"CntOut:inst\|inst2~53\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~53" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CntOut:inst\|inst2~52 " "Info: Detected gated clock \"CntOut:inst\|inst2~52\" as buffer" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CntOut.bdf" { { 136 296 360 184 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CntOut:inst\|inst2~52" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "SubDir:inst1\|8~155 " "Info: Detected gated clock \"SubDir:inst1\|8~155\" as buffer" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 480 728 792 552 "8" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SubDir:inst1\|8~155" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "SubDir:inst1\|8~151 " "Info: Detected gated clock \"SubDir:inst1\|8~151\" as buffer" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 480 728 792 552 "8" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SubDir:inst1\|8~151" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "SubDir:inst1\|37 " "Info: Detected ripple clock \"SubDir:inst1\|37\" as buffer" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 64 640 704 144 "37" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SubDir:inst1\|37" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "SubDir:inst1\|35 " "Info: Detected ripple clock \"SubDir:inst1\|35\" as buffer" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { -88 632 696 -8 "35" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SubDir:inst1\|35" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "SubDir:inst1\|38 " "Info: Detected ripple clock \"SubDir:inst1\|38\" as buffer" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 64 496 560 144 "38" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SubDir:inst1\|38" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "SubDir:inst1\|36 " "Info: Detected ripple clock \"SubDir:inst1\|36\" as buffer" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { -88 488 552 -8 "36" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SubDir:inst1\|36" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\] register lpm_dff1:inst2\|lpm_ff:lpm_ff_component\|dffs\[7\] 43.48 MHz 23.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 43.48 MHz between source register \"CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\]\" and destination register \"lpm_dff1:inst2\|lpm_ff:lpm_ff_component\|dffs\[7\]\" (period= 23.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\] 1 REG LC21 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 36; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns lpm_dff1:inst2\|lpm_ff:lpm_ff_component\|dffs\[7\] 2 REG LC11 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC11; Fanout = 1; REG Node = 'lpm_dff1:inst2\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns 83.33 % " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 16.67 % " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-13.000 ns - Smallest " "Info: - Smallest clock skew is -13.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { CLK } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 120 64 232 136 "CLK" "" } { 144 808 840 160 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_dff1:inst2\|lpm_ff:lpm_ff_component\|dffs\[7\] 2 REG LC11 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC11; Fanout = 1; REG Node = 'lpm_dff1:inst2\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "0.000 ns" { CLK lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "1.500 ns" { CLK lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.500 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { CLK } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 120 64 232 136 "CLK" "" } { 144 808 840 160 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns SubDir:inst1\|38 2 REG LC20 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC20; Fanout = 10; REG Node = 'SubDir:inst1\|38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "2.000 ns" { CLK SubDir:inst1|38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns SubDir:inst1\|8~151 3 COMB SEXP20 10 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = SEXP20; Fanout = 10; COMB Node = 'SubDir:inst1\|8~151'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { SubDir:inst1|38 SubDir:inst1|8~151 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 480 728 792 552 "8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 14.500 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\] 4 REG LC21 36 " "Info: 4: + IC(0.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = LC21; Fanout = 36; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "5.000 ns" { SubDir:inst1|8~151 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.500 ns 93.10 % " "Info: Total cell delay = 13.500 ns ( 93.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.90 % " "Info: Total interconnect delay = 1.000 ns ( 6.90 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.500 ns" { CLK SubDir:inst1|38 SubDir:inst1|8~151 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out SubDir:inst1|38 SubDir:inst1|8~151 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns 5.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "1.500 ns" { CLK lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.500 ns" { CLK SubDir:inst1|38 SubDir:inst1|8~151 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out SubDir:inst1|38 SubDir:inst1|8~151 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "1.500 ns" { CLK lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.500 ns" { CLK SubDir:inst1|38 SubDir:inst1|8~151 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out SubDir:inst1|38 SubDir:inst1|8~151 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns 5.000ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "A register CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] register CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 55.56 MHz 18.0 ns Internal " "Info: Clock \"A\" has Internal fmax of 55.56 MHz between source register \"CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]\" and destination register \"CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]\" (period= 18.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.000 ns + Longest register register " "Info: + Longest register to register delay is 14.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] 1 REG LC54 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC54; Fanout = 9; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|_~2982 2 COMB LC4 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC4; Fanout = 1; COMB Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|_~2982'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "8.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2982 } "NODE_NAME" } "" } } { "lpm_counter24.vhd" "" { Text "D:/altera/qdesigns50/GuangShanChi/lpm_counter24.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.000 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 3 REG LC57 5 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.000 ns; Loc. = LC57; Fanout = 5; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2982 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns 85.71 % " "Info: Total cell delay = 12.000 ns ( 85.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 14.29 % " "Info: Total interconnect delay = 2.000 ns ( 14.29 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2982 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2982 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 1.000ns 1.000ns } { 0.000ns 7.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "A destination 11.500 ns + Shortest register " "Info: + Shortest clock path from clock \"A\" to destination register is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns A 1 CLK PIN_85 6 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 6; CLK Node = 'A'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { A } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 104 64 232 120 "A" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns SubDir:inst1\|8~156 2 COMB SEXP53 7 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP53; Fanout = 7; COMB Node = 'SubDir:inst1\|8~156'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { A SubDir:inst1|8~156 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 480 728 792 552 "8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 11.500 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 3 REG LC57 5 " "Info: 3: + IC(0.000 ns) + CELL(5.000 ns) = 11.500 ns; Loc. = LC57; Fanout = 5; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "5.000 ns" { SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.500 ns 91.30 % " "Info: Total cell delay = 10.500 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 8.70 % " "Info: Total interconnect delay = 1.000 ns ( 8.70 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "11.500 ns" { A SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.500 ns" { A A~out SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 5.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "A source 11.500 ns - Longest register " "Info: - Longest clock path from clock \"A\" to source register is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns A 1 CLK PIN_85 6 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 6; CLK Node = 'A'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { A } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 104 64 232 120 "A" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns SubDir:inst1\|8~156 2 COMB SEXP53 7 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP53; Fanout = 7; COMB Node = 'SubDir:inst1\|8~156'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { A SubDir:inst1|8~156 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 480 728 792 552 "8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 11.500 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] 3 REG LC54 9 " "Info: 3: + IC(0.000 ns) + CELL(5.000 ns) = 11.500 ns; Loc. = LC54; Fanout = 9; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "5.000 ns" { SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.500 ns 91.30 % " "Info: Total cell delay = 10.500 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 8.70 % " "Info: Total interconnect delay = 1.000 ns ( 8.70 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "11.500 ns" { A SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.500 ns" { A A~out SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 5.000ns 5.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "11.500 ns" { A SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.500 ns" { A A~out SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 5.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "11.500 ns" { A SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.500 ns" { A A~out SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 5.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2982 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.000 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2982 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 1.000ns 1.000ns } { 0.000ns 7.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "11.500 ns" { A SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.500 ns" { A A~out SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 5.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "11.500 ns" { A SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.500 ns" { A A~out SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 5.000ns 5.000ns } } }  } 0}
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