subdir.tan.qmsg

光栅尺的四细分和辩向电路

{ "Info" "ITDB_TH_RESULT" "38 B clk -2.000 ns register " "Info: th for register \"38\" (data pin = \"B\", clock pin = \"clk\") is -2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { clk } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 8 112 280 24 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns 38 2 REG LC2 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "0.000 ns" { clk 38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 38 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns B 1 PIN PIN_85 6 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 6; PIN Node = 'B'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { B } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 80 112 280 96 "B" "" } { 424 152 248 440 "B" "" } { 256 152 248 272 "B" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns 38 2 REG LC2 9 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.000 ns" { B 38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.500 ns" { B 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { B B~out 38 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 38 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.500 ns" { B 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { B B~out 38 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 15 11:36:05 2007 " "Info: Processing ended: Fri Jun 15 11:36:05 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}