subdir.tan.qmsg

光栅尺的四细分和辩向电路

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 8 112 280 24 "clk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register 38 register 37 100.0 MHz 10.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 100.0 MHz between source register \"38\" and destination register \"37\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 38 1 REG LC2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 9; REG Node = '38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { 38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns 37 2 REG LC7 8 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC7; Fanout = 8; REG Node = '37'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.000 ns" { 38 37 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 640 704 144 "37" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns 83.33 % " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 16.67 % " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.000 ns" { 38 37 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { 38 37 } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { clk } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 8 112 280 24 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns 37 2 REG LC7 8 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC7; Fanout = 8; REG Node = '37'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "0.000 ns" { clk 37 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 640 704 144 "37" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 37 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 37 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { clk } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 8 112 280 24 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns 38 2 REG LC2 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "0.000 ns" { clk 38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 38 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 37 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 37 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 38 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 640 704 144 "37" "" } } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.000 ns" { 38 37 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { 38 37 } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 37 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 37 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 38 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "38 B clk 7.000 ns register " "Info: tsu for register \"38\" (data pin = \"B\", clock pin = \"clk\") is 7.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns B 1 PIN PIN_85 6 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 6; PIN Node = 'B'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { B } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 80 112 280 96 "B" "" } { 424 152 248 440 "B" "" } { 256 152 248 272 "B" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns 38 2 REG LC2 9 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.000 ns" { B 38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.500 ns" { B 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { B B~out 38 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { clk } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 8 112 280 24 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns 38 2 REG LC2 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "0.000 ns" { clk 38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 38 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "6.500 ns" { B 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { B B~out 38 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 38 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 38 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Pulse 36 13.000 ns register " "Info: tco from clock \"clk\" to destination pin \"Pulse\" through register \"36\" is 13.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { clk } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 8 112 280 24 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns 36 2 REG LC4 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4; Fanout = 9; REG Node = '36'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "0.000 ns" { clk 36 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { -88 488 552 -8 "36" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 36 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 36 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { -88 488 552 -8 "36" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns + Longest register pin " "Info: + Longest register to pin delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 36 1 REG LC4 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 9; REG Node = '36'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { 36 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { -88 488 552 -8 "36" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns inst4~9 2 COMB LC3 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'inst4~9'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "8.000 ns" { 36 inst4~9 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 408 752 816 456 "inst4" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 9.500 ns Pulse 3 PIN PIN_1 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'Pulse'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { inst4~9 Pulse } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 424 888 1064 440 "Pulse" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns 89.47 % " "Info: Total cell delay = 8.500 ns ( 89.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.53 % " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "9.500 ns" { 36 inst4~9 Pulse } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { 36 inst4~9 Pulse } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { clk 36 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out 36 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "9.500 ns" { 36 inst4~9 Pulse } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { 36 inst4~9 Pulse } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A DirClkB 10.000 ns Longest " "Info: Longest tpd from source pin \"A\" to destination pin \"DirClkB\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns A 1 PIN PIN_50 6 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_50; Fanout = 6; PIN Node = 'A'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "" { A } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { -72 112 280 -56 "A" "" } { 208 152 248 224 "A" "" } { 472 152 248 488 "A" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.500 ns 8~18 2 COMB LC5 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC5; Fanout = 1; COMB Node = '8~18'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "8.000 ns" { A 8~18 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 480 392 456 552 "8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 10.000 ns DirClkB 3 PIN PIN_100 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'DirClkB'" {  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "1.500 ns" { 8~18 DirClkB } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 512 520 696 528 "DirClkB" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir_cmp.qrpt" Compiler "SubDir" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/SubDir/db/SubDir.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/SubDir/" "" "10.000 ns" { A 8~18 DirClkB } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { A A~out 8~18 DirClkB } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 7.000ns 1.500ns } } }  } 0}