subdir.map.qmsg

光栅尺的四细分和辩向电路

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 15 11:36:01 2007 " "Info: Processing started: Fri Jun 15 11:36:01 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SubDir -c SubDir " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SubDir -c SubDir" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SubDir.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file SubDir.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SubDir " "Info: Found entity 1: SubDir" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SubDir " "Info: Elaborating entity \"SubDir\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "inst5 High " "Info: Power-up level of register \"inst5\" is not specified -- using power-up level of High to minimize register" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 480 776 840 560 "inst5" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "inst5 data_in VCC " "Warning: Reduced register \"inst5\" with stuck data_in port to stuck value VCC" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 480 776 840 560 "inst5" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "inst11 preset VCC " "Warning: Reduced register \"inst11\" with stuck preset port to stuck value VCC" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 272 768 832 352 "inst11" "" } } } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DirA VCC " "Warning: Pin \"DirA\" stuck at VCC" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir/SubDir.bdf" { { 288 976 1152 304 "DirA" "" } } } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "27 " "Info: Implemented 27 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "14 " "Info: Implemented 14 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 15 11:36:02 2007 " "Info: Processing ended: Fri Jun 15 11:36:02 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}