📄 subdir.fit.rpt
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; I/O Standard ; Load ; Termination Resistance ;
+--------------+-------+------------------------+
; LVTTL ; 10 pF ; Not Available ;
; LVCMOS ; 10 pF ; Not Available ;
; TTL ; 0 pF ; Not Available ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+----------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |SubDir ; 14 ; 17 ; |SubDir ;
+----------------------------+------------+------+---------------------+
+--------------------------------------------------------------------------------------+
; Control Signals ;
+------+----------+---------+-------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------+----------+---------+-------+--------+----------------------+------------------+
; clk ; PIN_87 ; 4 ; Clock ; yes ; On ; -- ;
+------+----------+---------+-------+--------+----------------------+------------------+
+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk ; PIN_87 ; 4 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+---------+-----------------------+
; Name ; Fan-Out ;
+---------+-----------------------+
; 38 ; 6 ;
; 36 ; 6 ;
; 37 ; 5 ;
; 35 ; 5 ;
; B ; 4 ;
; A ; 4 ;
; ~VCC~0 ; 1 ;
; inst4~9 ; 1 ;
; 8~18 ; 1 ;
; 7~18 ; 1 ;
; 15~10 ; 1 ;
; 16~10 ; 1 ;
; 14~10 ; 1 ;
; 13~10 ; 1 ;
; B~2 ; 1 ;
; A~2 ; 1 ;
+---------+-----------------------+
+----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-----------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 6 / 288 ( 2 % ) ;
; PIAs ; 6 / 288 ( 2 % ) ;
+----------------------------+-----------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 0.75) ; Number of LABs (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 1.75) ; Number of LABs (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 1 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+----------------------+---------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------+---------------------------------------+
; A ; LC8 ; A ; AN ;
; A ; LC9 ; B ; BN ;
; A ; LC4 ; clk, A ; 35, 13~10, 14~10, 7~18, 8~18, inst4~9 ;
; A ; LC2 ; clk, B ; 37, 16~10, 15~10, 7~18, 8~18, inst4~9 ;
; A ; LC10 ; clk, 36 ; 13~10, 14~10, 7~18, 8~18, inst4~9 ;
; A ; LC7 ; clk, 38 ; 16~10, 15~10, 7~18, 8~18, inst4~9 ;
; A ; LC11 ; 36, 35 ; AU ;
; A ; LC16 ; 36, 35 ; AD ;
; A ; LC14 ; 38, 37 ; BU ;
; A ; LC13 ; 38, 37 ; BD ;
; A ; LC6 ; 38, 37, A, 36, 35, B ; DirClkA ;
; A ; LC5 ; 36, 35, B, 38, 37, A ; DirClkB ;
; A ; LC3 ; 36, 35, 38, 37 ; Pulse ;
; A ; LC1 ; ; DirA ;
+-----+------------+----------------------+---------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Fri Jun 15 11:36:03 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SubDir -c SubDir
Info: Selected device EPM7128STC100-10 for design "SubDir"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Jun 15 11:36:03 2007
Info: Elapsed time: 00:00:01
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