subdir.tan.rpt

光栅尺的四细分和辩向电路

; N/A   ; None         ; 13.000 ns  ; 38   ; DirClkB ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 35   ; DirClkB ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 37   ; DirClkB ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 36   ; DirClkA ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 38   ; DirClkA ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 35   ; DirClkA ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 37   ; DirClkA ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 38   ; BD      ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 37   ; BD      ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 38   ; BU      ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 37   ; BU      ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 36   ; AD      ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 35   ; AD      ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 36   ; AU      ; clk        ;
; N/A   ; None         ; 13.000 ns  ; 35   ; AU      ; clk        ;
+-------+--------------+------------+------+---------+------------+


+--------------------------------------------------------------+
; tpd                                                          ;
+-------+-------------------+-----------------+------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To      ;
+-------+-------------------+-----------------+------+---------+
; N/A   ; None              ; 10.000 ns       ; A    ; DirClkB ;
; N/A   ; None              ; 10.000 ns       ; B    ; DirClkB ;
; N/A   ; None              ; 10.000 ns       ; A    ; DirClkA ;
; N/A   ; None              ; 10.000 ns       ; B    ; DirClkA ;
; N/A   ; None              ; 10.000 ns       ; B    ; BN      ;
; N/A   ; None              ; 10.000 ns       ; A    ; AN      ;
+-------+-------------------+-----------------+------+---------+


+----------------------------------------------------------------+
; th                                                             ;
+---------------+-------------+-----------+------+----+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+----+----------+
; N/A           ; None        ; -2.000 ns ; B    ; 38 ; clk      ;
; N/A           ; None        ; -2.000 ns ; A    ; 36 ; clk      ;
+---------------+-------------+-----------+------+----+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jun 15 11:36:05 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SubDir -c SubDir
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 100.0 MHz between source register "38" and destination register "37" (period= 10.0 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 9; REG Node = '38'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC7; Fanout = 8; REG Node = '37'
        Info: Total cell delay = 5.000 ns ( 83.33 % )
        Info: Total interconnect delay = 1.000 ns ( 16.67 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC7; Fanout = 8; REG Node = '37'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tsu for register "38" (data pin = "B", clock pin = "clk") is 7.000 ns
    Info: + Longest pin to register delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 6; PIN Node = 'B'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'
        Info: Total cell delay = 5.500 ns ( 84.62 % )
        Info: Total interconnect delay = 1.000 ns ( 15.38 % )
    Info: + Micro setup delay of destination is 2.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "Pulse" through register "36" is 13.000 ns
    Info: + Longest clock path from clock "clk" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4; Fanout = 9; REG Node = '36'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 9; REG Node = '36'
        Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'inst4~9'
        Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'Pulse'
        Info: Total cell delay = 8.500 ns ( 89.47 % )
        Info: Total interconnect delay = 1.000 ns ( 10.53 % )
Info: Longest tpd from source pin "A" to destination pin "DirClkB" is 10.000 ns
    Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_50; Fanout = 6; PIN Node = 'A'
    Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC5; Fanout = 1; COMB Node = '8~18'
    Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'DirClkB'
    Info: Total cell delay = 9.000 ns ( 90.00 % )
    Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: th for register "38" (data pin = "B", clock pin = "clk") is -2.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 3.000 ns
    Info: - Shortest pin to register delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 6; PIN Node = 'B'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 9; REG Node = '38'
        Info: Total cell delay = 5.500 ns ( 84.62 % )
        Info: Total interconnect delay = 1.000 ns ( 15.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jun 15 11:36:05 2007
    Info: Elapsed time: 00:00:00