📄 subdir.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L51 is A~2 at LC8
A1L51_or_out = !A;
A1L51 = A1L51_or_out;
--A1L02 is B~2 at LC9
A1L02_or_out = !B;
A1L02 = A1L02_or_out;
--36 is 36 at LC4
36_or_out = A;
36_reg_input = 36_or_out;
36 = DFFE(36_reg_input, GLOBAL(clk), , , );
--38 is 38 at LC2
38_or_out = B;
38_reg_input = 38_or_out;
38 = DFFE(38_reg_input, GLOBAL(clk), , , );
--35 is 35 at LC10
35_or_out = 36;
35_reg_input = 35_or_out;
35 = DFFE(35_reg_input, GLOBAL(clk), , , );
--37 is 37 at LC7
37_or_out = 38;
37_reg_input = 37_or_out;
37 = DFFE(37_reg_input, GLOBAL(clk), , , );
--A1L3 is 13~10 at LC11
A1L3_p1_out = 36 & !35;
A1L3_or_out = A1L3_p1_out;
A1L3 = A1L3_or_out;
--A1L4 is 14~10 at LC16
A1L4_p1_out = !36 & 35;
A1L4_or_out = A1L4_p1_out;
A1L4 = A1L4_or_out;
--A1L6 is 16~10 at LC14
A1L6_p1_out = 38 & !37;
A1L6_or_out = A1L6_p1_out;
A1L6 = A1L6_or_out;
--A1L5 is 15~10 at LC13
A1L5_p1_out = !38 & 37;
A1L5_or_out = A1L5_p1_out;
A1L5 = A1L5_or_out;
--A1L1 is 7~18 at LC6
A1L1_p1_out = !38 & 37 & A;
A1L1_p2_out = 36 & !35 & B;
A1L1_p3_out = 38 & !37 & !A;
A1L1_p4_out = !36 & 35 & !B;
A1L1_or_out = A1L1_p1_out # A1L1_p2_out # A1L1_p3_out # A1L1_p4_out;
A1L1 = !(A1L1_or_out);
--A1L2 is 8~18 at LC5
A1L2_p1_out = !36 & 35 & B;
A1L2_p2_out = 38 & !37 & A;
A1L2_p3_out = !38 & 37 & !A;
A1L2_p4_out = 36 & !35 & !B;
A1L2_or_out = A1L2_p1_out # A1L2_p2_out # A1L2_p3_out # A1L2_p4_out;
A1L2 = !(A1L2_or_out);
--A1L52 is inst4~9 at LC3
A1L52_p1_out = !36 & 35;
A1L52_p2_out = 38 & !37;
A1L52_p3_out = !38 & 37;
A1L52_p4_out = 36 & !35;
A1L52_or_out = A1L52_p1_out # A1L52_p2_out # A1L52_p3_out # A1L52_p4_out;
A1L52 = !(A1L52_or_out);
--~VCC~0 is ~VCC~0 at LC1
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);
--clk is clk at PIN_87
--operation mode is input
clk = INPUT();
--A is A at PIN_50
--operation mode is input
A = INPUT();
--B is B at PIN_85
--operation mode is input
B = INPUT();
--DirA is DirA at PIN_2
--operation mode is output
DirA = OUTPUT(~VCC~0);
--AN is AN at PIN_98
--operation mode is output
AN = OUTPUT(A1L51);
--BN is BN at PIN_97
--operation mode is output
BN = OUTPUT(A1L02);
--AU is AU at PIN_96
--operation mode is output
AU = OUTPUT(A1L3);
--AD is AD at PIN_92
--operation mode is output
AD = OUTPUT(A1L4);
--BU is BU at PIN_93
--operation mode is output
BU = OUTPUT(A1L6);
--BD is BD at PIN_94
--operation mode is output
BD = OUTPUT(A1L5);
--DirClkA is DirClkA at PIN_99
--operation mode is output
DirClkA = OUTPUT(A1L1);
--DirClkB is DirClkB at PIN_100
--operation mode is output
DirClkB = OUTPUT(A1L2);
--Pulse is Pulse at PIN_1
--operation mode is output
Pulse = OUTPUT(A1L52);
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