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📄 cutout.tan.qmsg

📁 光栅尺的四细分和辩向电路
💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[10\] Sclr DirCntA 10.000 ns register " "Info: tsu for register \"lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[10\]\" (data pin = \"Sclr\", clock pin = \"DirCntA\") is 10.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.500 ns + Longest pin register " "Info: + Longest pin to register delay is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns Sclr 1 PIN PIN_50 57 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_50; Fanout = 57; PIN Node = 'Sclr'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { Sclr } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { -24 56 224 -8 "Sclr" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|_~2926 2 COMB LC28 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC28; Fanout = 1; COMB Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|_~2926'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "8.000 ns" { Sclr lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2926 } "NODE_NAME" } "" } } { "lpm_counter24.vhd" "" { Text "D:/altera/qdesigns50/GuangShanChi/CutOut/lpm_counter24.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[10\] 3 REG LC34 28 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = LC34; Fanout = 28; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[10\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2926 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.500 ns 86.21 % " "Info: Total cell delay = 12.500 ns ( 86.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.79 % " "Info: Total interconnect delay = 2.000 ns ( 13.79 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "14.500 ns" { Sclr lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2926 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { Sclr Sclr~out lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2926 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } { 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 7.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DirCntA destination 6.500 ns - Shortest register " "Info: - Shortest clock path from clock \"DirCntA\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DirCntA 1 CLK PIN_85 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 25; CLK Node = 'DirCntA'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { DirCntA } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 160 56 224 176 "DirCntA" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[10\] 2 REG LC34 28 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC34; Fanout = 28; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[10\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "14.500 ns" { Sclr lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2926 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { Sclr Sclr~out lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2926 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } { 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 7.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[10] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "DirCntA Cnt8b\[7\] lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\] 18.000 ns register " "Info: tco from clock \"DirCntA\" to destination pin \"Cnt8b\[7\]\" through register \"lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\]\" is 18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DirCntA source 6.500 ns + Longest register " "Info: + Longest clock path from clock \"DirCntA\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DirCntA 1 CLK PIN_85 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 25; CLK Node = 'DirCntA'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { DirCntA } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 160 56 224 176 "DirCntA" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\] 2 REG LC24 35 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC24; Fanout = 35; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns + Longest register pin " "Info: + Longest register to pin delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\] 1 REG LC24 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC24; Fanout = 35; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[7\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns Mux:inst5\|lpm_mux:lpm_mux_component\|muxlut:\$00023\|result_node~58 2 COMB LC13 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC13; Fanout = 1; COMB Node = 'Mux:inst5\|lpm_mux:lpm_mux_component\|muxlut:\$00023\|result_node~58'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "8.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 } "NODE_NAME" } "" } } { "muxlut.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/muxlut.tdf" 169 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 9.500 ns Cnt8b\[7\] 3 PIN PIN_94 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_94; Fanout = 0; PIN Node = 'Cnt8b\[7\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "1.500 ns" { Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 Cnt8b[7] } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 168 1080 1256 184 "Cnt8b\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns 89.47 % " "Info: Total cell delay = 8.500 ns ( 89.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.53 % " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "9.500 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 Cnt8b[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 Cnt8b[7] } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "9.500 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 Cnt8b[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7] Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 Cnt8b[7] } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "OutSel\[1\] Cnt8b\[7\] 10.000 ns Longest " "Info: Longest tpd from source pin \"OutSel\[1\]\" to destination pin \"Cnt8b\[7\]\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns OutSel\[1\] 1 PIN PIN_5 24 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_5; Fanout = 24; PIN Node = 'OutSel\[1\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { OutSel[1] } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 416 72 240 432 "OutSel\[1\]" "" } { 456 72 240 472 "OutSel\[0\]" "" } { 248 896 976 264 "OutSel\[1..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.500 ns Mux:inst5\|lpm_mux:lpm_mux_component\|muxlut:\$00023\|result_node~58 2 COMB LC13 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC13; Fanout = 1; COMB Node = 'Mux:inst5\|lpm_mux:lpm_mux_component\|muxlut:\$00023\|result_node~58'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "8.000 ns" { OutSel[1] Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 } "NODE_NAME" } "" } } { "muxlut.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/muxlut.tdf" 169 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 10.000 ns Cnt8b\[7\] 3 PIN PIN_94 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = PIN_94; Fanout = 0; PIN Node = 'Cnt8b\[7\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "1.500 ns" { Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 Cnt8b[7] } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 168 1080 1256 184 "Cnt8b\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "10.000 ns" { OutSel[1] Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 Cnt8b[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { OutSel[1] OutSel[1]~out Mux:inst5|lpm_mux:lpm_mux_component|muxlut:$00023|result_node~58 Cnt8b[7] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 7.000ns 1.500ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\] Sclr DirCntA 3.000 ns register " "Info: th for register \"lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\]\" (data pin = \"Sclr\", clock pin = \"DirCntA\") is 3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DirCntA destination 6.500 ns + Longest register " "Info: + Longest clock path from clock \"DirCntA\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DirCntA 1 CLK PIN_85 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 25; CLK Node = 'DirCntA'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { DirCntA } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 160 56 224 176 "DirCntA" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\] 2 REG LC17 50 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC17; Fanout = 50; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns Sclr 1 PIN PIN_50 57 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_50; Fanout = 57; PIN Node = 'Sclr'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { Sclr } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { -24 56 224 -8 "Sclr" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\] 2 REG LC17 50 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC17; Fanout = 50; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { Sclr lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { Sclr lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { Sclr Sclr~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { Sclr lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { Sclr Sclr~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
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