📄 cutout.tan.qmsg

📁 光栅尺的四细分和辩向电路
💻 QMSG
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "DirCntB " "Info: Assuming node \"DirCntB\" is an undefined clock" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 144 56 224 160 "DirCntB" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DirCntB" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "DirCntA " "Info: Assuming node \"DirCntA\" is an undefined clock" {  } { { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 160 56 224 176 "DirCntA" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DirCntA" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "DirCntB register lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] register lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 55.56 MHz 18.0 ns Internal " "Info: Clock \"DirCntB\" has Internal fmax of 55.56 MHz between source register \"lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]\" and destination register \"lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]\" (period= 18.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.000 ns + Longest register register " "Info: + Longest register to register delay is 14.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] 1 REG LC48 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC48; Fanout = 8; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|_~2986 2 COMB LC15 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC15; Fanout = 1; COMB Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|_~2986'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "8.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 } "NODE_NAME" } "" } } { "lpm_counter24.vhd" "" { Text "D:/altera/qdesigns50/GuangShanChi/CutOut/lpm_counter24.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.000 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 3 REG LC39 4 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.000 ns; Loc. = LC39; Fanout = 4; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns 85.71 % " "Info: Total cell delay = 12.000 ns ( 85.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 14.29 % " "Info: Total interconnect delay = 2.000 ns ( 14.29 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "14.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 1.000ns 1.000ns } { 0.000ns 7.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DirCntB destination 6.500 ns + Shortest register " "Info: + Shortest clock path from clock \"DirCntB\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DirCntB 1 CLK PIN_27 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_27; Fanout = 25; CLK Node = 'DirCntB'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { DirCntB } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 144 56 224 160 "DirCntB" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 2 REG LC39 4 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC39; Fanout = 4; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { DirCntB lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntB lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntB DirCntB~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DirCntB source 6.500 ns - Longest register " "Info: - Longest clock path from clock \"DirCntB\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DirCntB 1 CLK PIN_27 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_27; Fanout = 25; CLK Node = 'DirCntB'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { DirCntB } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 144 56 224 160 "DirCntB" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] 2 REG LC48 8 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC48; Fanout = 8; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { DirCntB lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntB lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntB DirCntB~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntB lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntB DirCntB~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntB lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntB DirCntB~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "14.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 1.000ns 1.000ns } { 0.000ns 7.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntB lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntB DirCntB~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntB lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntB DirCntB~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "DirCntA register lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] register lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 55.56 MHz 18.0 ns Internal " "Info: Clock \"DirCntA\" has Internal fmax of 55.56 MHz between source register \"lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]\" and destination register \"lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]\" (period= 18.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.000 ns + Longest register register " "Info: + Longest register to register delay is 14.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] 1 REG LC48 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC48; Fanout = 8; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|_~2986 2 COMB LC15 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC15; Fanout = 1; COMB Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|_~2986'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "8.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 } "NODE_NAME" } "" } } { "lpm_counter24.vhd" "" { Text "D:/altera/qdesigns50/GuangShanChi/CutOut/lpm_counter24.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.000 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 3 REG LC39 4 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.000 ns; Loc. = LC39; Fanout = 4; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns 85.71 % " "Info: Total cell delay = 12.000 ns ( 85.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 14.29 % " "Info: Total interconnect delay = 2.000 ns ( 14.29 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "14.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 1.000ns 1.000ns } { 0.000ns 7.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DirCntA destination 6.500 ns + Shortest register " "Info: + Shortest clock path from clock \"DirCntA\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DirCntA 1 CLK PIN_85 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 25; CLK Node = 'DirCntA'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { DirCntA } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 160 56 224 176 "DirCntA" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\] 2 REG LC39 4 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC39; Fanout = 4; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[22\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DirCntA source 6.500 ns - Longest register " "Info: - Longest clock path from clock \"DirCntA\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DirCntA 1 CLK PIN_85 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 25; CLK Node = 'DirCntA'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "" { DirCntA } "NODE_NAME" } "" } } { "CntOut.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/CutOut/CntOut.bdf" { { 160 56 224 176 "DirCntA" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\] 2 REG LC48 8 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC48; Fanout = 8; REG Node = 'lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[20\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.000 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "14.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.000 ns" { lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] lpm_counter24:inst|lpm_counter:lpm_counter_component|_~2986 lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 1.000ns 1.000ns } { 0.000ns 7.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut_cmp.qrpt" Compiler "CutOut" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/CutOut/db/CutOut.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/CutOut/" "" "6.500 ns" { DirCntA lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DirCntA DirCntA~out lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[20] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
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