guangshanchi.tan.rpt

光栅尺的四细分和辩向电路

; Total number of failed paths ;       ;               ;                                  ;                                                                           ;                                                                           ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7128STC100-10   ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; A               ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                      ; To                                                                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[7]  ; lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7]                            ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[15] ; lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7]                            ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] ; lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[7]                            ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[6]  ; lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[6]                            ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[14] ; lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[6]                            ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[22] ; lpm_dff1:inst2|lpm_ff:lpm_ff_component|dffs[6]                            ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;