count10.rpt
来自「等精度频率计的verilogHDL的实现,我花了好长时间才写的哦」· RPT 代码 · 共 1,486 行 · 第 1/5 页
RPT
1,486 行
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\frequent\count10.rpt
count10
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
98 - - B -- OUTPUT 0 1 0 0 cout
116 - - - 07 OUTPUT 0 1 0 0 out0
10 - - B -- OUTPUT 0 1 0 0 out1
112 - - - 04 OUTPUT 0 1 0 0 out2
111 - - - 03 OUTPUT 0 1 0 0 out3
68 - - - 07 OUTPUT 0 1 0 0 out4
100 - - A -- OUTPUT 0 1 0 0 out5
91 - - D -- OUTPUT 0 1 0 0 out6
64 - - - 10 OUTPUT 0 1 0 0 out7
21 - - D -- OUTPUT 0 1 0 0 out8
19 - - D -- OUTPUT 0 1 0 0 out9
23 - - D -- OUTPUT 0 1 0 0 out10
22 - - D -- OUTPUT 0 1 0 0 out11
79 - - F -- OUTPUT 0 1 0 0 out12
80 - - F -- OUTPUT 0 1 0 0 out13
81 - - F -- OUTPUT 0 1 0 0 out14
82 - - F -- OUTPUT 0 1 0 0 out15
32 - - F -- OUTPUT 0 1 0 0 out16
31 - - F -- OUTPUT 0 1 0 0 out17
30 - - F -- OUTPUT 0 1 0 0 out18
33 - - F -- OUTPUT 0 1 0 0 out19
17 - - C -- OUTPUT 0 1 0 0 out20
18 - - C -- OUTPUT 0 1 0 0 out21
12 - - C -- OUTPUT 0 1 0 0 out22
13 - - C -- OUTPUT 0 1 0 0 out23
39 - - - 33 OUTPUT 0 1 0 0 out24
141 - - - 33 OUTPUT 0 1 0 0 out25
133 - - - 28 OUTPUT 0 1 0 0 out26
136 - - - 30 OUTPUT 0 1 0 0 out27
109 - - - 01 OUTPUT 0 1 0 0 out28
99 - - B -- OUTPUT 0 1 0 0 out29
118 - - - 09 OUTPUT 0 1 0 0 out30
9 - - B -- OUTPUT 0 1 0 0 out31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\frequent\count10.rpt
count10
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 03 AND2 0 2 0 1 |lpm_add_sub:557|addcore:adder|:55
- 7 - B 12 AND2 0 2 0 1 |lpm_add_sub:558|addcore:adder|:55
- 7 - D 26 AND2 0 2 0 1 |lpm_add_sub:559|addcore:adder|:55
- 7 - F 16 AND2 0 2 0 1 |lpm_add_sub:560|addcore:adder|:55
- 5 - F 34 AND2 0 2 0 1 |lpm_add_sub:561|addcore:adder|:55
- 7 - C 28 AND2 0 2 0 1 |lpm_add_sub:562|addcore:adder|:55
- 5 - B 21 AND2 0 2 0 1 |lpm_add_sub:563|addcore:adder|:55
- 6 - B 15 AND2 0 2 0 1 |lpm_add_sub:564|addcore:adder|:55
- 1 - B 03 AND2 0 4 0 2 :40
- 5 - B 01 AND2 s 1 1 0 3 ~57~1
- 7 - B 03 OR2 0 4 0 1 :57
- 3 - B 03 OR2 0 4 0 1 :58
- 2 - B 34 OR2 0 3 0 1 :59
- 8 - B 03 DFFE + 2 1 0 3 :78
- 5 - B 03 DFFE + 2 1 0 4 :79
- 3 - B 34 DFFE + 2 1 0 5 :80
- 1 - B 07 DFFE + 2 0 0 5 :81
- 5 - B 07 DFFE + 2 1 0 5 cout1 (:93)
- 5 - B 12 AND2 0 4 0 2 :97
- 2 - B 12 AND2 s 1 1 0 3 ~114~1
- 8 - B 12 OR2 0 4 0 1 :114
- 6 - B 12 OR2 0 4 0 1 :115
- 7 - B 07 OR2 0 3 0 1 :116
- 4 - B 12 DFFE 2 2 0 3 :135
- 3 - B 12 DFFE 2 2 0 4 :136
- 3 - B 07 DFFE 2 2 0 5 :137
- 2 - B 07 DFFE 2 1 0 5 :138
- 1 - B 12 DFFE 2 2 0 5 cout2 (:150)
- 2 - D 26 AND2 0 4 0 2 :154
- 6 - D 27 AND2 s 1 1 0 3 ~171~1
- 8 - D 26 OR2 0 4 0 1 :171
- 6 - D 26 OR2 0 4 0 1 :172
- 5 - D 26 OR2 0 3 0 1 :173
- 1 - D 26 DFFE 2 2 0 3 out33 (:192)
- 4 - D 26 DFFE 2 2 0 4 out32 (:193)
- 3 - D 26 DFFE 2 2 0 5 :194
- 5 - D 27 DFFE 2 1 0 5 :195
- 2 - D 27 DFFE 2 2 0 5 cout3 (:207)
- 1 - F 16 AND2 0 4 0 2 :211
- 6 - F 16 AND2 s 1 1 0 3 ~228~1
- 8 - F 16 OR2 0 4 0 1 :228
- 4 - F 16 OR2 0 4 0 1 :229
- 3 - F 03 OR2 0 3 0 1 :230
- 5 - F 16 DFFE 2 2 0 3 out43 (:249)
- 3 - F 16 DFFE 2 2 0 4 out42 (:250)
- 2 - F 03 DFFE 2 2 0 5 out41 (:251)
- 1 - F 03 DFFE 2 1 0 5 out40 (:252)
- 2 - F 16 DFFE 2 2 0 5 cout4 (:264)
- 3 - F 34 AND2 0 4 0 2 :268
- 6 - F 34 AND2 s 1 1 0 3 ~285~1
- 7 - F 34 OR2 0 4 0 1 :285
- 4 - F 34 OR2 0 4 0 1 :286
- 4 - F 24 OR2 0 3 0 1 :287
- 8 - F 34 DFFE 2 2 0 3 out53 (:306)
- 2 - F 34 DFFE 2 2 0 4 out52 (:307)
- 3 - F 24 DFFE 2 2 0 5 out51 (:308)
- 1 - F 24 DFFE 2 1 0 5 out50 (:309)
- 1 - F 34 DFFE 2 2 0 5 cout5 (:321)
- 3 - C 28 AND2 0 4 0 2 :325
- 1 - C 28 AND2 s 1 1 0 3 ~342~1
- 8 - C 28 OR2 0 4 0 1 :342
- 6 - C 28 OR2 0 4 0 1 :343
- 3 - C 31 OR2 0 3 0 1 :344
- 5 - C 28 DFFE 2 2 0 3 out63 (:363)
- 4 - C 28 DFFE 2 2 0 4 out62 (:364)
- 2 - C 31 DFFE 2 2 0 5 out61 (:365)
- 1 - C 31 DFFE 2 1 0 5 out60 (:366)
- 2 - C 28 DFFE 2 2 0 5 cout6 (:378)
- 2 - B 21 AND2 0 4 0 2 :382
- 1 - B 21 AND2 s 1 1 0 3 ~399~1
- 6 - B 21 OR2 0 4 0 1 :399
- 3 - B 21 OR2 0 4 0 1 :400
- 7 - B 34 OR2 0 3 0 1 :401
- 8 - B 21 DFFE 2 2 0 3 out73 (:420)
- 4 - B 21 DFFE 2 2 0 4 out72 (:421)
- 6 - B 34 DFFE 2 2 0 5 out71 (:422)
- 8 - B 34 DFFE 2 1 0 5 out70 (:423)
- 7 - B 21 DFFE 2 2 0 5 cout7 (:435)
- 8 - B 15 OR2 ! 0 4 0 2 :439
- 3 - B 01 AND2 s 1 1 0 3 ~456~1
- 7 - B 15 OR2 0 4 0 1 :456
- 5 - B 15 OR2 0 4 0 1 :457
- 1 - B 15 OR2 0 3 0 1 :458
- 2 - B 15 DFFE 2 2 0 3 out83 (:477)
- 4 - B 15 DFFE 2 2 0 4 out82 (:478)
- 3 - B 15 DFFE 2 2 0 5 out81 (:479)
- 4 - B 01 DFFE 2 1 0 5 out80 (:480)
- 2 - B 22 DFFE + 0 1 1 0 :513
- 1 - B 09 DFFE + 0 1 1 0 :514
- 3 - B 17 DFFE + 0 1 1 0 :515
- 1 - B 01 DFFE + 0 1 1 0 :516
- 2 - B 29 DFFE + 0 1 1 0 :517
- 1 - B 28 DFFE + 0 1 1 0 :518
- 4 - B 34 DFFE + 0 1 1 0 :519
- 1 - B 34 DFFE + 0 1 1 0 :520
- 3 - C 33 DFFE + 0 1 1 0 :521
- 2 - C 27 DFFE + 0 1 1 0 :522
- 7 - C 31 DFFE + 0 1 1 0 :523
- 6 - C 31 DFFE + 0 1 1 0 :524
- 7 - F 19 DFFE + 0 1 1 0 :525
- 1 - F 20 DFFE + 0 1 1 0 :526
- 2 - F 24 DFFE + 0 1 1 0 :527
- 5 - F 24 DFFE + 0 1 1 0 :528
- 1 - F 04 DFFE + 0 1 1 0 :529
- 2 - F 01 DFFE + 0 1 1 0 :530
- 4 - F 03 DFFE + 0 1 1 0 :531
- 6 - F 03 DFFE + 0 1 1 0 :532
- 6 - D 21 DFFE + 0 1 1 0 :533
- 7 - D 35 DFFE + 0 1 1 0 :534
- 1 - D 24 DFFE + 0 1 1 0 :535
- 4 - D 27 DFFE + 0 1 1 0 :536
- 2 - B 10 DFFE + 0 1 1 0 :537
- 2 - D 18 DFFE + 0 1 1 0 :538
- 8 - B 07 DFFE + 0 1 1 0 :539
- 4 - B 07 DFFE + 0 1 1 0 :540
- 2 - B 03 DFFE + 0 1 1 0 :541
- 4 - B 03 DFFE + 0 1 1 0 :542
- 5 - B 34 DFFE + 0 1 1 0 :543
- 6 - B 07 DFFE + 0 1 1 0 :544
- 6 - B 01 DFFE 2 2 1 0 :556
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\frequent\count10.rpt
count10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 23/144( 15%) 2/ 72( 2%) 2/ 72( 2%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 6/144( 4%) 0/ 72( 0%) 4/ 72( 5%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 8/144( 5%) 1/ 72( 1%) 4/ 72( 5%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 12/144( 8%) 4/ 72( 5%) 4/ 72( 5%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\frequent\count10.rpt
count10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 37 clk
DFF 6 cout1
DFF 6 cout2
DFF 6 cout3
DFF 6 cout4
DFF 6 cout5
DFF 6 cout6
DFF 6 cout7
Device-Specific Information: e:\frequent\count10.rpt
count10
** EQUATIONS **
clk : INPUT;
clr : INPUT;
en : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC6_B1;
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