fre_ctr.ndb

等精度频率计的verilogHDL的实现,我花了好长时间才写的哦

NDB006
The number of symbol table entries is: 1
The length of the symbol table is: 13

Index Hierarchy Path
----- --------------
!	&null_hpath&

The number of name info structs is : 20

InsOrder BitField SymTableIndex NextSyn SynParent Loc ChainType NextChain ChainParent FanOut DirExp ParExp ShareExp NodeName
-------- -------- ------------- ------- --------- --- --------- --------- ----------- ------ ------ ------ -------- --------
"	IeEA	!	9	0	:10	v
#	L8e}	!	4	0	3	3	*	#	:11	w
$	IeEA	!	13	0	:12	x
%	IeEA	!	7	0	:13	y
&	IeEA	!	9	0	:14	z
'	IeEA	!	10	0	:15	{
(	IeEA	!	10	0	:16	|
)	IeEA	!	10	0	:17	}
*	L8e}	!	4	0	2	4	+	:18	~
+	L8f/	!	13	0	1	2	:19	"!
,	IeEA	!	13	0	:20	""
-	IeEA	!	7	0	:6	r
.	IeEA	!	8	0	:7	s
/	IeEA	!	9	0	:8	t
0	IeEA	!	9	0	:9	u
1	(@\6H	!	3	0	3	+	#	*	clk	m
2	IeE[	!	2	0	count_clr	p
3	IeE[	!	4	0	count_en	o
4	IeE[	!	4	0	load	q
5	L8ef	!	3	0	2	#	*	rst	n