frequent1.v

来自「等精度频率计的verilogHDL的实现,我花了好长时间才写的哦」· Verilog 代码 · 共 17 行

module	frequent1(qout,cout,signal,clk,rst);
output[31:0] qout;
output	cout;
input	signal,clk,rst;
reg[31:0]	qout;
reg		cout;
//reg[31:0]		din;
wire[31:0]  din;
//wire

fre_ctr ctr1(clk,rst,count_en,count_clr,load);
count10	c1(din,cout,count_en,count_clr,signal);
//not	n1(notout,clk);
//a1(andout,notout,load);
latch_32 l1(qout,din,load);//andout
endmodule