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📄 frequent1.rpt

📁 等精度频率计的verilogHDL的实现,我花了好长时间才写的哦
💻 RPT
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字号:
   -      2     -    B    01       DFFE   +            0    1    0    1  |count10:c1|:527
   -      1     -    B    01       DFFE   +            0    1    0    1  |count10:c1|:528
   -      2     -    B    04       DFFE   +            0    1    0    1  |count10:c1|:529
   -      3     -    B    06       DFFE   +            0    1    0    1  |count10:c1|:530
   -      2     -    B    06       DFFE   +            0    1    0    1  |count10:c1|:531
   -      4     -    B    08       DFFE   +            0    1    0    1  |count10:c1|:532
   -      3     -    B    08       DFFE   +            0    1    0    1  |count10:c1|:533
   -      1     -    B    09       DFFE   +            0    1    0    1  |count10:c1|:534
   -      2     -    B    28       DFFE   +            0    1    0    1  |count10:c1|:535
   -      3     -    F    31       DFFE   +            0    1    0    1  |count10:c1|:536
   -      2     -    B    33       DFFE   +            0    1    0    1  |count10:c1|:537
   -      1     -    B    33       DFFE   +            0    1    0    1  |count10:c1|:538
   -      1     -    B    35       DFFE   +            0    1    0    1  |count10:c1|:539
   -      5     -    B    36       DFFE   +            0    1    0    1  |count10:c1|:540
   -      2     -    B    36       DFFE   +            0    1    0    1  |count10:c1|:541
   -      4     -    B    29       DFFE   +            0    1    0    1  |count10:c1|:542
   -      5     -    B    31       DFFE   +            0    1    0    1  |count10:c1|:543
   -      2     -    B    29       DFFE   +            0    1    0    1  |count10:c1|:544
   -      7     -    B    26       DFFE                0    4    1    0  |count10:c1|:556
   -      2     -    B    26       DFFE   +            1    0    0   49  |fre_ctr:ctr1|:11
   -      6     -    B    26       DFFE   +            1    1    0   33  |fre_ctr:ctr1|:18
   -      6     -    B    31       AND2                1    1    0   40  |fre_ctr:ctr1|:19
   -      4     -    B    36       DFFE                0    2    1    0  |latch_32:l1|:98
   -      8     -    B    29       DFFE                0    2    1    0  |latch_32:l1|:99
   -      1     -    B    31       DFFE                0    2    1    0  |latch_32:l1|:100
   -      3     -    B    29       DFFE                0    2    1    0  |latch_32:l1|:101
   -      5     -    B    33       DFFE                0    2    1    0  |latch_32:l1|:102
   -      6     -    B    01       DFFE                0    2    1    0  |latch_32:l1|:103
   -      8     -    B    28       DFFE                0    2    1    0  |latch_32:l1|:104
   -      1     -    B    28       DFFE                0    2    1    0  |latch_32:l1|:105
   -      4     -    B    28       DFFE                0    2    1    0  |latch_32:l1|:106
   -      8     -    F    31       DFFE                0    2    1    0  |latch_32:l1|:107
   -      1     -    F    31       DFFE                0    2    1    0  |latch_32:l1|:108
   -      2     -    F    31       DFFE                0    2    1    0  |latch_32:l1|:109
   -      4     -    F    31       DFFE                0    2    1    0  |latch_32:l1|:110
   -      6     -    B    33       DFFE                0    2    1    0  |latch_32:l1|:111
   -      8     -    B    01       DFFE                0    2    1    0  |latch_32:l1|:112
   -      3     -    B    01       DFFE                0    2    1    0  |latch_32:l1|:113
   -      1     -    B    04       DFFE                0    2    1    0  |latch_32:l1|:114
   -      4     -    B    06       DFFE                0    2    1    0  |latch_32:l1|:115
   -      1     -    B    06       DFFE                0    2    1    0  |latch_32:l1|:116
   -      1     -    B    08       DFFE                0    2    1    0  |latch_32:l1|:117
   -      2     -    B    08       DFFE                0    2    1    0  |latch_32:l1|:118
   -      2     -    B    09       DFFE                0    2    1    0  |latch_32:l1|:119
   -      3     -    B    28       DFFE                0    2    1    0  |latch_32:l1|:120
   -      7     -    F    31       DFFE                0    2    1    0  |latch_32:l1|:121
   -      4     -    B    33       DFFE                0    2    1    0  |latch_32:l1|:122
   -      3     -    B    33       DFFE                0    2    1    0  |latch_32:l1|:123
   -      4     -    B    35       DFFE                0    2    1    0  |latch_32:l1|:124
   -      3     -    B    36       DFFE                0    2    1    0  |latch_32:l1|:125
   -      6     -    B    36       DFFE                0    2    1    0  |latch_32:l1|:126
   -      5     -    B    29       DFFE                0    2    1    0  |latch_32:l1|:127
   -      3     -    B    31       DFFE                0    2    1    0  |latch_32:l1|:128
   -      1     -    B    29       DFFE                0    2    1    0  |latch_32:l1|:129


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register


Device-Specific Information:                         e:\frequent\frequent1.rpt
frequent1

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/144(  0%)     0/ 72(  0%)     0/ 72(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:      53/144( 36%)     0/ 72(  0%)     3/ 72(  4%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       3/144(  2%)     0/ 72(  0%)     0/ 72(  0%)    1/16(  6%)      2/16( 12%)     0/16(  0%)
D:       4/144(  2%)     1/ 72(  1%)     0/ 72(  0%)    0/16(  0%)      5/16( 31%)     0/16(  0%)
E:       3/144(  2%)     0/ 72(  0%)     1/ 72(  1%)    0/16(  0%)      4/16( 25%)     0/16(  0%)
F:      12/144(  8%)     1/ 72(  1%)     8/ 72( 11%)    0/16(  0%)      9/16( 56%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
02:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
06:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
07:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
08:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
09:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
25:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
26:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
27:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
28:      4/24( 16%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
29:      4/24( 16%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
30:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
31:      5/24( 20%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
32:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
33:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
34:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
35:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
36:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                         e:\frequent\frequent1.rpt
frequent1

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       37         signal
DFF         33         |fre_ctr:ctr1|:18
DFF          6         |count10:c1|cout1
DFF          6         |count10:c1|cout2
DFF          6         |count10:c1|cout3
DFF          6         |count10:c1|cout4
DFF          6         |count10:c1|cout5
DFF          6         |count10:c1|cout6
DFF          6         |count10:c1|cout7
INPUT        3         clk


Device-Specific Information:                         e:\frequent\frequent1.rpt
frequent1

** EQUATIONS **

clk      : INPUT;
rst      : INPUT;
signal   : INPUT;

-- Node name is 'cout' 
-- Equation name is 'cout', type is output 
cout     =  _LC7_B26;

-- Node name is 'qout0' 
-- Equation name is 'qout0', type is output 
qout0    =  _LC1_B29;

-- Node name is 'qout1' 
-- Equation name is 'qout1', type is output 
qout1    =  _LC3_B31;

-- Node name is 'qout2' 
-- Equation name is 'qout2', type is output 
qout2    =  _LC5_B29;

-- Node name is 'qout3' 
-- Equation name is 'qout3', type is output 
qout3    =  _LC6_B36;

-- Node name is 'qout4' 
-- Equation name is 'qout4', type is output 
qout4    =  _LC3_B36;

-- Node name is 'qout5' 
-- Equation name is 'qout5', type is output 
qout5    =  _LC4_B35;

-- Node name is 'qout6' 
-- Equation name is 'qout6', type is output 
qout6    =  _LC3_B33;

-- Node name is 'qout7' 
-- Equation name is 'qout7', type is output 
qout7    =  _LC4_B33;

-- Node name is 'qout8' 
-- Equation name is 'qout8', type is output 
qout8    =  _LC7_F31;

-- Node name is 'qout9' 
-- Equation name is 'qout9', type is output 
qout9    =  _LC3_B28;

-- Node name is 'qout10' 
-- Equation name is 'qout10', type is output 
qout10   =  _LC2_B9;

-- Node name is 'qout11' 
-- Equation name is 'qout11', type is output 
qout11   =  _LC2_B8;

-- Node name is 'qout12' 
-- Equation name is 'qout12', type is output 
qout12   =  _LC1_B8;

-- Node name is 'qout13' 
-- Equation name is 'qout13', type is output 
qout13   =  _LC1_B6;

-- Node name is 'qout14' 
-- Equation name is 'qout14', type is output 
qout14   =  _LC4_B6;

-- Node name is 'qout15' 
-- Equation name is 'qout15', type is output 
qout15   =  _LC1_B4;

-- Node name is 'qout16' 
-- Equation name is 'qout16', type is output 
qout16   =  _LC3_B1;

-- Node name is 'qout17' 
-- Equation name is 'qout17', type is output 
qout17   =  _LC8_B1;

-- Node name is 'qout18' 
-- Equation name is 'qout18', type is output 
qout18   =  _LC6_B33;

-- Node name is 'qout19' 
-- Equation name is 'qout19', type is output 
qout19   =  _LC4_F31;

-- Node name is 'qout20' 
-- Equation name is 'qout20', type is output 
qout20   =  _LC2_F31;

-- Node name is 'qout21' 
-- Equation name is 'qout21', type is output 
qout21   =  _LC1_F31;

-- Node name is 'qout22' 
-- Equation name is 'qout22', type is output 
qout22   =  _LC8_F31;

-- Node name is 'qout23' 
-- Equation name is 'qout23', type is output 
qout23   =  _LC4_B28;

-- Node name is 'qout24' 
-- Equation name is 'qout24', type is output 
qout24   =  _LC1_B28;

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