📄 frequent1.rpt
字号:
B18 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
B19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 6/22( 27%)
B21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
B22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
B23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
B25 4/ 8( 50%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 5/22( 22%)
B26 3/ 8( 37%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 4/22( 18%)
B27 6/ 8( 75%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 5/22( 22%)
B28 7/ 8( 87%) 4/ 8( 50%) 0/ 8( 0%) 2/2 0/2 5/22( 22%)
B29 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 2/2 0/2 5/22( 22%)
B30 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
B31 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 0/2 6/22( 27%)
B33 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 2/2 0/2 5/22( 22%)
B35 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 2/22( 9%)
B36 7/ 8( 87%) 3/ 8( 37%) 1/ 8( 12%) 2/2 0/2 5/22( 22%)
F30 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
F31 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 6/22( 27%)
F35 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 34/96 ( 35%)
Total logic cells used: 155/1728 ( 8%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.41/4 ( 60%)
Total fan-in: 374/6912 ( 5%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 33
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 155
Total flipflops required: 106
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 8/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 6 8 0 2 0 4 0 4 2 0 0 0 0 7 0 0 0 8 0 8 0 8 8 8 0 4 3 6 7 8 8 8 0 8 0 2 7 134/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 0 5 0 21/0
Total: 6 8 0 2 0 4 0 4 2 0 0 0 0 7 0 0 0 8 0 8 0 8 8 8 0 4 3 6 7 8 16 16 0 8 0 7 7 155/0
Device-Specific Information: e:\frequent\frequent1.rpt
frequent1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT G ^ 0 0 0 1 clk
13 - - C -- INPUT ^ 0 0 0 2 rst
126 - - - -- INPUT G ^ 0 0 0 0 signal
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\frequent\frequent1.rpt
frequent1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
29 - - E -- OUTPUT 0 1 0 0 cout
30 - - F -- OUTPUT 0 1 0 0 qout0
31 - - F -- OUTPUT 0 1 0 0 qout1
32 - - F -- OUTPUT 0 1 0 0 qout2
33 - - F -- OUTPUT 0 1 0 0 qout3
36 - - - 36 OUTPUT 0 1 0 0 qout4
37 - - - 35 OUTPUT 0 1 0 0 qout5
38 - - - 34 OUTPUT 0 1 0 0 qout6
39 - - - 33 OUTPUT 0 1 0 0 qout7
41 - - - 31 OUTPUT 0 1 0 0 qout8
42 - - - 28 OUTPUT 0 1 0 0 qout9
65 - - - 09 OUTPUT 0 1 0 0 qout10
67 - - - 08 OUTPUT 0 1 0 0 qout11
68 - - - 07 OUTPUT 0 1 0 0 qout12
69 - - - 06 OUTPUT 0 1 0 0 qout13
70 - - - 05 OUTPUT 0 1 0 0 qout14
72 - - - 03 OUTPUT 0 1 0 0 qout15
73 - - - 01 OUTPUT 0 1 0 0 qout16
78 - - F -- OUTPUT 0 1 0 0 qout17
79 - - F -- OUTPUT 0 1 0 0 qout18
80 - - F -- OUTPUT 0 1 0 0 qout19
81 - - F -- OUTPUT 0 1 0 0 qout20
82 - - F -- OUTPUT 0 1 0 0 qout21
83 - - E -- OUTPUT 0 1 0 0 qout22
86 - - E -- OUTPUT 0 1 0 0 qout23
87 - - E -- OUTPUT 0 1 0 0 qout24
88 - - D -- OUTPUT 0 1 0 0 qout25
89 - - D -- OUTPUT 0 1 0 0 qout26
90 - - D -- OUTPUT 0 1 0 0 qout27
91 - - D -- OUTPUT 0 1 0 0 qout28
92 - - D -- OUTPUT 0 1 0 0 qout29
95 - - C -- OUTPUT 0 1 0 0 qout30
96 - - C -- OUTPUT 0 1 0 0 qout31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\frequent\frequent1.rpt
frequent1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 31 AND2 0 2 0 1 |count10:c1|lpm_add_sub:557|addcore:adder|:55
- 1 - B 36 AND2 0 2 0 1 |count10:c1|lpm_add_sub:558|addcore:adder|:55
- 7 - B 30 AND2 0 2 0 1 |count10:c1|lpm_add_sub:559|addcore:adder|:55
- 7 - B 02 AND2 0 2 0 1 |count10:c1|lpm_add_sub:560|addcore:adder|:55
- 4 - B 14 AND2 0 2 0 1 |count10:c1|lpm_add_sub:561|addcore:adder|:55
- 7 - F 30 AND2 0 2 0 1 |count10:c1|lpm_add_sub:562|addcore:adder|:55
- 2 - B 27 AND2 0 2 0 1 |count10:c1|lpm_add_sub:563|addcore:adder|:55
- 5 - B 22 AND2 0 2 0 1 |count10:c1|lpm_add_sub:564|addcore:adder|:55
- 5 - B 23 AND2 0 4 0 2 |count10:c1|:40
- 8 - B 23 AND2 s 0 2 0 3 |count10:c1|~57~1
- 7 - B 23 OR2 0 4 0 1 |count10:c1|:57
- 6 - B 23 OR2 0 4 0 1 |count10:c1|:58
- 4 - B 31 OR2 0 3 0 1 |count10:c1|:59
- 3 - B 23 DFFE + 0 3 0 3 |count10:c1|out13 (|count10:c1|:78)
- 4 - B 23 DFFE + 0 3 0 4 |count10:c1|out12 (|count10:c1|:79)
- 8 - B 31 DFFE + 0 3 0 5 |count10:c1|out11 (|count10:c1|:80)
- 1 - B 23 DFFE + 0 2 0 5 |count10:c1|out10 (|count10:c1|:81)
- 2 - B 23 DFFE + 0 3 0 5 |count10:c1|cout1 (|count10:c1|:93)
- 1 - B 21 AND2 0 4 0 2 |count10:c1|:97
- 6 - B 14 AND2 s 0 2 0 3 |count10:c1|~114~1
- 8 - B 21 OR2 0 4 0 1 |count10:c1|:114
- 7 - B 21 OR2 0 4 0 1 |count10:c1|:115
- 6 - B 21 OR2 0 3 0 1 |count10:c1|:116
- 4 - B 21 DFFE 0 4 0 3 |count10:c1|out23 (|count10:c1|:135)
- 3 - B 21 DFFE 0 4 0 4 |count10:c1|out22 (|count10:c1|:136)
- 5 - B 21 DFFE 0 4 0 5 |count10:c1|out21 (|count10:c1|:137)
- 2 - B 21 DFFE 0 3 0 5 |count10:c1|out20 (|count10:c1|:138)
- 4 - B 25 DFFE 0 4 0 5 |count10:c1|cout2 (|count10:c1|:150)
- 2 - B 30 AND2 0 4 0 2 |count10:c1|:154
- 3 - B 25 AND2 s 0 2 0 3 |count10:c1|~171~1
- 8 - B 30 OR2 0 4 0 1 |count10:c1|:171
- 4 - B 30 OR2 0 4 0 1 |count10:c1|:172
- 3 - B 30 OR2 0 3 0 1 |count10:c1|:173
- 5 - B 30 DFFE 0 4 0 3 |count10:c1|out33 (|count10:c1|:192)
- 6 - B 30 DFFE 0 4 0 4 |count10:c1|out32 (|count10:c1|:193)
- 1 - B 30 DFFE 0 4 0 5 |count10:c1|out31 (|count10:c1|:194)
- 2 - B 25 DFFE 0 3 0 5 |count10:c1|out30 (|count10:c1|:195)
- 8 - B 25 DFFE 0 4 0 5 |count10:c1|cout3 (|count10:c1|:207)
- 2 - B 02 AND2 0 4 0 2 |count10:c1|:211
- 1 - B 14 AND2 s 0 2 0 3 |count10:c1|~228~1
- 8 - B 02 OR2 0 4 0 1 |count10:c1|:228
- 6 - B 02 OR2 0 4 0 1 |count10:c1|:229
- 5 - B 02 OR2 0 3 0 1 |count10:c1|:230
- 4 - B 02 DFFE 0 4 0 3 |count10:c1|out43 (|count10:c1|:249)
- 1 - B 02 DFFE 0 4 0 4 |count10:c1|out42 (|count10:c1|:250)
- 3 - B 02 DFFE 0 4 0 5 |count10:c1|out41 (|count10:c1|:251)
- 3 - B 14 DFFE 0 3 0 5 |count10:c1|out40 (|count10:c1|:252)
- 2 - B 14 DFFE 0 4 0 5 |count10:c1|cout4 (|count10:c1|:264)
- 2 - B 18 AND2 0 4 0 2 |count10:c1|:268
- 8 - B 18 AND2 s 0 2 0 3 |count10:c1|~285~1
- 7 - B 18 OR2 0 4 0 1 |count10:c1|:285
- 5 - B 18 OR2 0 4 0 1 |count10:c1|:286
- 5 - B 14 OR2 0 3 0 1 |count10:c1|:287
- 4 - B 18 DFFE 0 4 0 3 |count10:c1|out53 (|count10:c1|:306)
- 6 - B 18 DFFE 0 4 0 4 |count10:c1|out52 (|count10:c1|:307)
- 8 - B 14 DFFE 0 4 0 5 |count10:c1|out51 (|count10:c1|:308)
- 3 - B 18 DFFE 0 3 0 5 |count10:c1|out50 (|count10:c1|:309)
- 1 - B 18 DFFE 0 4 0 5 |count10:c1|cout5 (|count10:c1|:321)
- 2 - F 30 AND2 0 4 0 2 |count10:c1|:325
- 3 - F 30 AND2 s 0 2 0 3 |count10:c1|~342~1
- 8 - F 30 OR2 0 4 0 1 |count10:c1|:342
- 5 - F 30 OR2 0 4 0 1 |count10:c1|:343
- 4 - F 35 OR2 0 3 0 1 |count10:c1|:344
- 4 - F 30 DFFE 0 4 0 3 |count10:c1|out63 (|count10:c1|:363)
- 6 - F 30 DFFE 0 4 0 4 |count10:c1|out62 (|count10:c1|:364)
- 8 - F 35 DFFE 0 4 0 5 |count10:c1|out61 (|count10:c1|:365)
- 2 - F 35 DFFE 0 3 0 5 |count10:c1|out60 (|count10:c1|:366)
- 1 - F 30 DFFE 0 4 0 5 |count10:c1|cout6 (|count10:c1|:378)
- 2 - B 19 OR2 ! 0 4 0 2 |count10:c1|:382
- 8 - B 19 AND2 s 0 2 0 3 |count10:c1|~399~1
- 7 - B 19 OR2 0 4 0 1 |count10:c1|:399
- 4 - B 19 OR2 0 4 0 1 |count10:c1|:400
- 6 - B 27 OR2 0 3 0 1 |count10:c1|:401
- 6 - B 19 DFFE 0 4 0 3 |count10:c1|out73 (|count10:c1|:420)
- 3 - B 19 DFFE 0 4 0 4 |count10:c1|out72 (|count10:c1|:421)
- 1 - B 27 DFFE 0 4 0 5 |count10:c1|out71 (|count10:c1|:422)
- 5 - B 27 DFFE 0 3 0 5 |count10:c1|out70 (|count10:c1|:423)
- 1 - B 19 DFFE 0 4 0 5 |count10:c1|cout7 (|count10:c1|:435)
- 6 - B 22 OR2 ! 0 4 0 2 |count10:c1|:439
- 3 - B 27 AND2 s 0 2 0 3 |count10:c1|~456~1
- 7 - B 22 OR2 0 4 0 1 |count10:c1|:456
- 3 - B 22 OR2 0 4 0 1 |count10:c1|:457
- 1 - B 22 OR2 0 3 0 1 |count10:c1|:458
- 2 - B 22 DFFE 0 4 0 3 |count10:c1|out83 (|count10:c1|:477)
- 8 - B 22 DFFE 0 4 0 4 |count10:c1|out82 (|count10:c1|:478)
- 4 - B 22 DFFE 0 4 0 5 |count10:c1|out81 (|count10:c1|:479)
- 5 - B 19 DFFE 0 3 0 5 |count10:c1|out80 (|count10:c1|:480)
- 7 - B 36 DFFE + 0 1 0 1 |count10:c1|:513
- 7 - B 29 DFFE + 0 1 0 1 |count10:c1|:514
- 7 - B 31 DFFE + 0 1 0 1 |count10:c1|:515
- 6 - B 29 DFFE + 0 1 0 1 |count10:c1|:516
- 8 - B 33 DFFE + 0 1 0 1 |count10:c1|:517
- 4 - B 01 DFFE + 0 1 0 1 |count10:c1|:518
- 6 - B 28 DFFE + 0 1 0 1 |count10:c1|:519
- 4 - B 27 DFFE + 0 1 0 1 |count10:c1|:520
- 5 - B 28 DFFE + 0 1 0 1 |count10:c1|:521
- 6 - F 31 DFFE + 0 1 0 1 |count10:c1|:522
- 1 - F 35 DFFE + 0 1 0 1 |count10:c1|:523
- 3 - F 35 DFFE + 0 1 0 1 |count10:c1|:524
- 5 - F 31 DFFE + 0 1 0 1 |count10:c1|:525
- 7 - B 33 DFFE + 0 1 0 1 |count10:c1|:526
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