lattice.prj

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

[PROJECT_INFORMATION]
Version=5.2
Project_Name=frequent
Project_Directory=C:\My Documents\shudianku
SW_VERSION=8.2

[SOURCE_INFORMATION]
Design_Directory=C:\My Documents\shudianku\frequent
Design_File=frequent.edf
Design_Type=EDF
Parameter_File=
Design_Modified=991465954
Design=FREQUENT

[DATABASE_INFORMATION]
Database_File=frequent.LDB

[SETTING_INFORMATION]
Settings_File=frequent.stp
Last Setting=

[EDIF Setting]
VCC=VCC
GND=GND
Property_File=
EDIF reader Vendor change=1
EDIF reader Vendor=VIEWlogic
EDIF writer Vendor=
Psnttn=0
LPMAttr=0
Cell Prefix=
Load Default Setting=1
Ground floating Output pins=1
Async Clear=0
Async Preset=0
Map Clock Enable=0
Array Index Ordering=-array_index_up
Least Significant Bit=-array_lsb_left
Extension=edo

[PROJECT_NEW_UPDATE]
PART=ispLSI1032E-70LJ84

[Extended UI]
Option=