frequent.syn

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

JDF B
// Created by Version 8.2 
PROJECT Untitled
DESIGN frequent Normal
DEVKIT ispLSI1032E-70LJ84
ENTRY Schematic/VHDL
MODULE frequent.vhd
MODSTYLE frequent Normal