frequent.tcl

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file .\frequent.TCL
#-- Written on Sat Jun 02 15:12:08 2001


#-- begin a new section
project -new

#-- Device options
set_option -technology pLSI

#-- add_file options
add_file -vhdl -lib work "frequent.vhd"

#-- top module name
set_option -top_module frequent

#simulation options
set_option -write_verilog true
set_option -write_vhdl true

#-- set result format/file last
project -result_file "frequent.edn"

#-- error message log file
project -log_file frequent.log

#-- let's save it
project -save frequent.tc_

#-- run Synplify
project -run

#-- **************************************************

#-- exit from Synplify
exit