fir_top.csf.qmsg

logic lock 的vhdl源码

{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "ser_ctrl_nc " "Warning: Found the following files while searching for definition of entity ser_ctrl_nc, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ser_ctrl_nc.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ser_ctrl_nc.v" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[11\]~reg0 fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[12\]~reg0 " "Info: Duplicate register fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[11\]~reg0 merged to single register fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[12\]~reg0" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/sadd.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/sadd.v" 10 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[13\]~reg0 fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[12\]~reg0 " "Info: Duplicate register fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[13\]~reg0 merged to single register fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[12\]~reg0" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/sadd.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/sadd.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fir_top_st:fir_top_st_component\|sym_add_ser:sym_18_n\|c_out data_in GND " "Warning: Reduced register fir_top_st:fir_top_st_component\|sym_add_ser:sym_18_n\|c_out with stuck data_in port to stuck value GND" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/sym_add_ser.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/sym_add_ser.v" 80 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_1_n\|sft02_n\[12\] fir_top_st:fir_top_st_component\|sym_add_ser:sym_18_n\|data_out\[0\]~reg0 " "Info: Duplicate register fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_1_n\|sft02_n\[12\] merged to single register fir_top_st:fir_top_st_component\|sym_add_ser:sym_18_n\|data_out\[0\]~reg0" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/lc_tdl_strat.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/lc_tdl_strat.v" 99 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v" 73 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "746 " "Info: Implemented 746 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "14 " "Info: Implemented 14 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "29 " "Info: Implemented 29 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "665 " "Info: Implemented 665 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "38 " "Info: Implemented 38 RAM segments" {  } {  } 0}  } {  } 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "lc_tdl " "Warning: Ignored assignments for entity \"lc_tdl\" -- entity does not exist in design" {  } {  } 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "lc_tdl_en " "Warning: Ignored assignments for entity \"lc_tdl_en\" -- entity does not exist in design" {  } {  } 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "lc_tdl_mr " "Warning: Ignored assignments for entity \"lc_tdl_mr\" -- entity does not exist in design" {  } {  } 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "sadd_lpm " "Warning: Ignored assignments for entity \"sadd_lpm\" -- entity does not exist in design" {  } {  } 0}