fir_top.csf.qmsg

logic lock 的vhdl源码

{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "sym_add_ser " "Warning: Found the following files while searching for definition of entity sym_add_ser, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/sym_add_ser.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/sym_add_ser.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_lut.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_lut.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ram_lut " "Info: Found entity 1: ram_lut" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/ram_lut.v" "ram_lut" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/ram_lut.v" 37 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "ram_lut " "Warning: Found the following files while searching for definition of entity ram_lut, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_lut.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_lut.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ram_2pt_var " "Info: Found entity 1: ram_2pt_var" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v" "ram_2pt_var" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v" 37 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "ram_2pt_var " "Warning: Found the following files while searching for definition of entity ram_2pt_var, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_2pt_var.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_2pt_var.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../../quartus4_0/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file ../../../../../../quartus4_0/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "c:/quartus4_0/libraries/megafunctions/altsyncram.tdf" "altsyncram" "" { Text "c:/quartus4_0/libraries/megafunctions/altsyncram.tdf" 430 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qs41.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_qs41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qs41 " "Info: Found entity 1: altsyncram_qs41" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" "altsyncram_qs41" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rs41.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_rs41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rs41 " "Info: Found entity 1: altsyncram_rs41" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_rs41.tdf" "altsyncram_rs41" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_rs41.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6m41.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_6m41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6m41 " "Info: Found entity 1: altsyncram_6m41" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_6m41.tdf" "altsyncram_6m41" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_6m41.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/sadd.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/sadd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sadd " "Info: Found entity 1: sadd" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/sadd.v" "sadd" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/sadd.v" 1 -1 0 } }  } 0}  } {  } 0}