fir_top.tan.qmsg

logic lock 的vhdl源码

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock fir_result\[24\] fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[24\]~reg0 6.881 ns register " "Info: Minimum tco from clock clock to destination pin fir_result\[24\] through register fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[24\]~reg0 is 6.881 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.037 ns + Shortest register " "Info: + Shortest clock path from clock clock to source register is 3.037 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 815 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 815; CLK Node = 'clock'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.815 ns) + CELL(0.560 ns) 3.037 ns fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[24\]~reg0 2 REG LC_X5_Y4_N8 1 " "Info: 2: + IC(1.815 ns) + CELL(0.560 ns) = 3.037 ns; Loc. = LC_X5_Y4_N8; Fanout = 1; REG Node = 'fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[24\]~reg0'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "2.375 ns" { clock fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0 } "NODE_NAME" } } } { "c:/megacore/fir_compiler-v2.7.1/lib/scale_shft_comb.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/scale_shft_comb.v" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.24 % " "Info: Total cell delay = 1.222 ns ( 40.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.815 ns 59.76 % " "Info: Total interconnect delay = 1.815 ns ( 59.76 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.037 ns" { clock fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/scale_shft_comb.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/scale_shft_comb.v" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.668 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[24\]~reg0 1 REG LC_X5_Y4_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N8; Fanout = 1; REG Node = 'fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[24\]~reg0'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0 } "NODE_NAME" } } } { "c:/megacore/fir_compiler-v2.7.1/lib/scale_shft_comb.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/scale_shft_comb.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.168 ns) + CELL(2.500 ns) 3.668 ns fir_result\[24\] 2 PIN Pin_Y2 0 " "Info: 2: + IC(1.168 ns) + CELL(2.500 ns) = 3.668 ns; Loc. = Pin_Y2; Fanout = 0; PIN Node = 'fir_result\[24\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.668 ns" { fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0 fir_result[24] } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 68.16 % " "Info: Total cell delay = 2.500 ns ( 68.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.168 ns 31.84 % " "Info: Total interconnect delay = 1.168 ns ( 31.84 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.668 ns" { fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0 fir_result[24] } "NODE_NAME" } } }  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.037 ns" { clock fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.668 ns" { fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0 fir_result[24] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 19 13:07:37 2004 " "Info: Processing ended: Thu Feb 19 13:07:37 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}