fir_top.tan.qmsg

logic lock 的vhdl源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock memory fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_datain_reg12 memory fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_memory_reg12 255.56 MHz 3.913 ns Internal " "Info: Clock clock has Internal fmax of 255.56 MHz between source memory fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_datain_reg12 and destination memory fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_memory_reg12 (period= 3.913 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.284 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_datain_reg12 1 MEM M4K_X15_Y2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y2; Fanout = 1; MEM Node = 'fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_datain_reg12'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.284 ns) 3.284 ns fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_memory_reg12 2 MEM M4K_X15_Y2 0 " "Info: 2: + IC(0.000 ns) + CELL(3.284 ns) = 3.284 ns; Loc. = M4K_X15_Y2; Fanout = 0; MEM Node = 'fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_memory_reg12'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.284 ns" { fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg12 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.284 ns 100.00 % " "Info: Total cell delay = 3.284 ns ( 100.00 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.284 ns" { fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg12 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.013 ns - Smallest " "Info: - Smallest clock skew is -0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.030 ns + Shortest memory " "Info: + Shortest clock path from clock clock to destination memory is 3.030 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 815 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 815; CLK Node = 'clock'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.812 ns) + CELL(0.556 ns) 3.030 ns fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_memory_reg12 2 MEM M4K_X15_Y2 0 " "Info: 2: + IC(1.812 ns) + CELL(0.556 ns) = 3.030 ns; Loc. = M4K_X15_Y2; Fanout = 0; MEM Node = 'fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_memory_reg12'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "2.368 ns" { clock fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg12 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.218 ns 40.20 % " "Info: Total cell delay = 1.218 ns ( 40.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.812 ns 59.80 % " "Info: Total interconnect delay = 1.812 ns ( 59.80 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.030 ns" { clock fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg12 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.043 ns - Longest memory " "Info: - Longest clock path from clock clock to source memory is 3.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 815 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 815; CLK Node = 'clock'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.812 ns) + CELL(0.569 ns) 3.043 ns fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_datain_reg12 2 MEM M4K_X15_Y2 1 " "Info: 2: + IC(1.812 ns) + CELL(0.569 ns) = 3.043 ns; Loc. = M4K_X15_Y2; Fanout = 1; MEM Node = 'fir_top_st:fir_top_st_component\|ram_lut:Ur0_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_qs41:auto_generated\|ram_block1a0~porta_datain_reg12'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "2.381 ns" { clock fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.231 ns 40.45 % " "Info: Total cell delay = 1.231 ns ( 40.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.812 ns 59.55 % " "Info: Total interconnect delay = 1.812 ns ( 59.55 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.043 ns" { clock fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 } "NODE_NAME" } } }  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.030 ns" { clock fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg12 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.043 ns" { clock fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.467 ns + " "Info: + Micro clock to output delay of source is 0.467 ns" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.149 ns + " "Info: + Micro setup delay of destination is 0.149 ns" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" 42 2 0 } }  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.284 ns" { fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg12 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.030 ns" { clock fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg12 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.043 ns" { clock fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[4\] data_in\[4\] clock 2.507 ns register " "Info: tsu for register fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[4\] (data pin = data_in\[4\], clock pin = clock) is 2.507 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.545 ns + Longest pin register " "Info: + Longest pin to register delay is 5.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns data_in\[4\] 1 PIN Pin_AD2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_AD2; Fanout = 1; PIN Node = 'data_in\[4\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { data_in[4] } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.334 ns) + CELL(0.235 ns) 5.545 ns fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[4\] 2 REG LC_X3_Y1_N7 1 " "Info: 2: + IC(4.334 ns) + CELL(0.235 ns) = 5.545 ns; Loc. = LC_X3_Y1_N7; Fanout = 1; REG Node = 'fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[4\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "4.569 ns" { data_in[4] fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4] } "NODE_NAME" } } } { "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.211 ns 21.84 % " "Info: Total cell delay = 1.211 ns ( 21.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.334 ns 78.16 % " "Info: Total interconnect delay = 4.334 ns ( 78.16 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "5.545 ns" { data_in[4] fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" 35 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.048 ns - Shortest register " "Info: - Shortest clock path from clock clock to destination register is 3.048 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 815 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 815; CLK Node = 'clock'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.826 ns) + CELL(0.560 ns) 3.048 ns fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[4\] 2 REG LC_X3_Y1_N7 1 " "Info: 2: + IC(1.826 ns) + CELL(0.560 ns) = 3.048 ns; Loc. = LC_X3_Y1_N7; Fanout = 1; REG Node = 'fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[4\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "2.386 ns" { clock fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4] } "NODE_NAME" } } } { "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.09 % " "Info: Total cell delay = 1.222 ns ( 40.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.826 ns 59.91 % " "Info: Total interconnect delay = 1.826 ns ( 59.91 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.048 ns" { clock fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4] } "NODE_NAME" } } }  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "5.545 ns" { data_in[4] fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4] } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.048 ns" { clock fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock rdy_to_ld fir_top_st:fir_top_st_component\|ser_ctrl_nc:Usc\|tdl_wait\[12\] 8.052 ns register " "Info: tco from clock clock to destination pin rdy_to_ld through register fir_top_st:fir_top_st_component\|ser_ctrl_nc:Usc\|tdl_wait\[12\] is 8.052 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.037 ns + Longest register " "Info: + Longest clock path from clock clock to source register is 3.037 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 815 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 815; CLK Node = 'clock'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.815 ns) + CELL(0.560 ns) 3.037 ns fir_top_st:fir_top_st_component\|ser_ctrl_nc:Usc\|tdl_wait\[12\] 2 REG LC_X12_Y4_N5 21 " "Info: 2: + IC(1.815 ns) + CELL(0.560 ns) = 3.037 ns; Loc. = LC_X12_Y4_N5; Fanout = 21; REG Node = 'fir_top_st:fir_top_st_component\|ser_ctrl_nc:Usc\|tdl_wait\[12\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "2.375 ns" { clock fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12] } "NODE_NAME" } } } { "c:/megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v" 83 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.24 % " "Info: Total cell delay = 1.222 ns ( 40.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.815 ns 59.76 % " "Info: Total interconnect delay = 1.815 ns ( 59.76 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.037 ns" { clock fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v" 83 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.839 ns + Longest register pin " "Info: + Longest register to pin delay is 4.839 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fir_top_st:fir_top_st_component\|ser_ctrl_nc:Usc\|tdl_wait\[12\] 1 REG LC_X12_Y4_N5 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y4_N5; Fanout = 21; REG Node = 'fir_top_st:fir_top_st_component\|ser_ctrl_nc:Usc\|tdl_wait\[12\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12] } "NODE_NAME" } } } { "c:/megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v" 83 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.081 ns) + CELL(2.758 ns) 4.839 ns rdy_to_ld 2 PIN Pin_AF3 0 " "Info: 2: + IC(2.081 ns) + CELL(2.758 ns) = 4.839 ns; Loc. = Pin_AF3; Fanout = 0; PIN Node = 'rdy_to_ld'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "4.839 ns" { fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12] rdy_to_ld } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.758 ns 57.00 % " "Info: Total cell delay = 2.758 ns ( 57.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.081 ns 43.00 % " "Info: Total interconnect delay = 2.081 ns ( 43.00 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "4.839 ns" { fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12] rdy_to_ld } "NODE_NAME" } } }  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.037 ns" { clock fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12] } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "4.839 ns" { fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12] rdy_to_ld } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[9\] data_in\[9\] clock -2.021 ns register " "Info: th for register fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[9\] (data pin = data_in\[9\], clock pin = clock) is -2.021 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.048 ns + Longest register " "Info: + Longest clock path from clock clock to destination register is 3.048 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 815 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 815; CLK Node = 'clock'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.826 ns) + CELL(0.560 ns) 3.048 ns fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[9\] 2 REG LC_X3_Y1_N3 1 " "Info: 2: + IC(1.826 ns) + CELL(0.560 ns) = 3.048 ns; Loc. = LC_X3_Y1_N3; Fanout = 1; REG Node = 'fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[9\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "2.386 ns" { clock fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9] } "NODE_NAME" } } } { "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.09 % " "Info: Total cell delay = 1.222 ns ( 40.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.826 ns 59.91 % " "Info: Total interconnect delay = 1.826 ns ( 59.91 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.048 ns" { clock fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" 35 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.169 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.169 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.093 ns) 1.093 ns data_in\[9\] 1 PIN Pin_AC4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.093 ns) = 1.093 ns; Loc. = Pin_AC4; Fanout = 1; PIN Node = 'data_in\[9\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { data_in[9] } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.841 ns) + CELL(0.235 ns) 5.169 ns fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[9\] 2 REG LC_X3_Y1_N3 1 " "Info: 2: + IC(3.841 ns) + CELL(0.235 ns) = 5.169 ns; Loc. = LC_X3_Y1_N3; Fanout = 1; REG Node = 'fir_top_st:fir_top_st_component\|par_ld_ser_tdl_nc:Utdl_0_a\|data_reg\[9\]'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "4.076 ns" { data_in[9] fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9] } "NODE_NAME" } } } { "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" "" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns 25.69 % " "Info: Total cell delay = 1.328 ns ( 25.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.841 ns 74.31 % " "Info: Total interconnect delay = 3.841 ns ( 74.31 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "5.169 ns" { data_in[9] fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9] } "NODE_NAME" } } }  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.048 ns" { clock fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9] } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "5.169 ns" { data_in[9] fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9] } "NODE_NAME" } } }  } 0}