fir_top.fit.qmsg

logic lock 的vhdl源码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 19 13:07:27 2004 " "Info: Processing ended: Thu Feb 19 13:07:27 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:54 " "Info: Elapsed time: 00:00:54" {  } {  } 0}  } {  } 0}