fir_top.fit.qmsg

logic lock 的vhdl源码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "1 " "Info: Fitter placement preparation operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.284 ns memory memory " "Info: Estimated most critical path is memory to memory delay of 3.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~porta_datain_reg0 1 MEM M4K_X15_Y3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y3; Fanout = 1; MEM Node = 'fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "" { fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_6m41.tdf" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_6m41.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.284 ns) 3.284 ns fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~porta_memory_reg0 2 MEM M4K_X15_Y3 0 " "Info: 2: + IC(0.000 ns) + CELL(3.284 ns) = 3.284 ns; Loc. = M4K_X15_Y3; Fanout = 0; MEM Node = 'fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.284 ns" { fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_datain_reg0 fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } } { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_6m41.tdf" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_6m41.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.284 ns 100.00 % " "Info: Total cell delay = 3.284 ns ( 100.00 % )" {  } {  } 0}  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" "" "" { Report "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top_cmp.qrpt" Compiler "fir_top" "UNKNOWN" "V1" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/fir_top.quartus_db" { Floorplan "" "" "3.284 ns" { fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_datain_reg0 fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "4 " "Info: Fitter placement operations ending: elapsed time = 4 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}