fir_top.fit.qmsg

logic lock 的vhdl源码

{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clock Global clock in Pin M24 " "Info: Automatically promoted signal clock to use Global clock in Pin M24" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 45 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock in Pin M26 " "Info: Automatically promoted signal rst to use Global clock in Pin M26" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 46 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}