fir_top_hier_info

logic lock 的vhdl源码

clk => sft14_n[7].CLK
clk => sft14_n[6].CLK
clk => sft14_n[5].CLK
clk => sft14_n[4].CLK
clk => sft14_n[3].CLK
clk => sft14_n[2].CLK
clk => sft14_n[1].CLK
clk => sft14_n[0].CLK
clk => sft15_n[12].CLK
clk => sft15_n[11].CLK
clk => sft15_n[10].CLK
clk => sft15_n[9].CLK
clk => sft15_n[8].CLK
clk => sft15_n[7].CLK
clk => sft15_n[6].CLK
clk => sft15_n[5].CLK
clk => sft15_n[4].CLK
clk => sft15_n[3].CLK
clk => sft15_n[2].CLK
clk => sft15_n[1].CLK
clk => sft15_n[0].CLK
clk => sft00_n[12].CLK
data_in => sft00_n[12].DATAIN
data_out[0] <= sft00_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= sft01_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= sft02_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= sft03_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= sft04_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= sft05_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= sft06_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= sft07_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= sft08_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= sft09_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= sft10_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= sft11_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= sft12_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= sft13_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= sft14_n[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= sft15_n[0].DB_MAX_OUTPUT_PORT_TYPE
rd_addr[0] <= <GND>
rd_addr[1] <= <GND>
rd_addr[2] <= <GND>
rd_addr[3] <= <GND>
wr_addr[0] <= <GND>
wr_addr[1] <= <GND>
wr_addr[2] <= <GND>
wr_addr[3] <= <GND>
ntdl <= sft15_n[0].DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_0_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_1_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_2_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_3_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_4_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_5_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_6_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_7_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_8_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_9_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_10_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_11_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_12_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_13_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_14_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_15_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_16_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_17_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|sym_add_ser:sym_18_n
rst => i8.OUTPUTSELECT
clk => c_out.CLK
clk => data_out[0]~reg0.CLK
a_in[0] => i~0.IN1
b_in[0] => i~0.IN2
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fir_top|fir_top_st:fir_top_st_component|ram_lut:Ur0_n
data_in[0] => data_in[0]~12.IN1
data_in[1] => data_in[1]~11.IN1
data_in[2] => data_in[2]~10.IN1
data_in[3] => data_in[3]~9.IN1
data_in[4] => data_in[4]~8.IN1
data_in[5] => data_in[5]~7.IN1
data_in[6] => data_in[6]~6.IN1
data_in[7] => data_in[7]~5.IN1
data_in[8] => data_in[8]~4.IN1
data_in[9] => data_in[9]~3.IN1
data_in[10] => data_in[10]~2.IN1
data_in[11] => data_in[11]~1.IN1
data_in[12] => data_in[12]~0.IN1
wr_en => wr_en~0.IN1
addr_in[0] => addr_in[0]~7.IN1
addr_in[1] => addr_in[1]~6.IN1
addr_in[2] => addr_in[2]~5.IN1
addr_in[3] => addr_in[3]~4.IN1
addr_in[4] => addr_in[4]~3.IN1
addr_in[5] => addr_in[5]~2.IN1
addr_in[6] => addr_in[6]~1.IN1
addr_in[7] => addr_in[7]~0.IN1
wr_addr[0] => wr_addr[0]~7.IN1
wr_addr[1] => wr_addr[1]~6.IN1
wr_addr[2] => wr_addr[2]~5.IN1
wr_addr[3] => wr_addr[3]~4.IN1
wr_addr[4] => wr_addr[4]~3.IN1
wr_addr[5] => wr_addr[5]~2.IN1
wr_addr[6] => wr_addr[6]~1.IN1
wr_addr[7] => wr_addr[7]~0.IN1
clk_in => clk_in~0.IN1
clk_out => clk_out~0.IN1
data_out[0] <= ram_2pt_var:ram.q
data_out[1] <= ram_2pt_var:ram.q
data_out[2] <= ram_2pt_var:ram.q
data_out[3] <= ram_2pt_var:ram.q
data_out[4] <= ram_2pt_var:ram.q
data_out[5] <= ram_2pt_var:ram.q
data_out[6] <= ram_2pt_var:ram.q
data_out[7] <= ram_2pt_var:ram.q
data_out[8] <= ram_2pt_var:ram.q
data_out[9] <= ram_2pt_var:ram.q
data_out[10] <= ram_2pt_var:ram.q
data_out[11] <= ram_2pt_var:ram.q
data_out[12] <= ram_2pt_var:ram.q


|fir_top|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram
data[0] => data[0]~12.IN1
data[1] => data[1]~11.IN1
data[2] => data[2]~10.IN1
data[3] => data[3]~9.IN1
data[4] => data[4]~8.IN1
data[5] => data[5]~7.IN1
data[6] => data[6]~6.IN1
data[7] => data[7]~5.IN1
data[8] => data[8]~4.IN1
data[9] => data[9]~3.IN1
data[10] => data[10]~2.IN1
data[11] => data[11]~1.IN1
data[12] => data[12]~0.IN1
wren => wren~0.IN1
wraddress[0] => wraddress[0]~7.IN1
wraddress[1] => wraddress[1]~6.IN1
wraddress[2] => wraddress[2]~5.IN1
wraddress[3] => wraddress[3]~4.IN1
wraddress[4] => wraddress[4]~3.IN1
wraddress[5] => wraddress[5]~2.IN1
wraddress[6] => wraddress[6]~1.IN1
wraddress[7] => wraddress[7]~0.IN1
rdaddress[0] => rdaddress[0]~7.IN1
rdaddress[1] => rdaddress[1]~6.IN1
rdaddress[2] => rdaddress[2]~5.IN1
rdaddress[3] => rdaddress[3]~4.IN1
rdaddress[4] => rdaddress[4]~3.IN1
rdaddress[5] => rdaddress[5]~2.IN1
rdaddress[6] => rdaddress[6]~1.IN1
rdaddress[7] => rdaddress[7]~0.IN1
wrclock => wrclock~0.IN1
rdclock => rdclock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b
q[8] <= altsyncram:altsyncram_component.q_b
q[9] <= altsyncram:altsyncram_component.q_b
q[10] <= altsyncram:altsyncram_component.q_b
q[11] <= altsyncram:altsyncram_component.q_b
q[12] <= altsyncram:altsyncram_component.q_b


|fir_top|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component
wren_a => altsyncram_qs41:auto_generated.wren_a
data_a[0] => altsyncram_qs41:auto_generated.data_a[0]
data_a[1] => altsyncram_qs41:auto_generated.data_a[1]
data_a[2] => altsyncram_qs41:auto_generated.data_a[2]
data_a[3] => altsyncram_qs41:auto_generated.data_a[3]
data_a[4] => altsyncram_qs41:auto_generated.data_a[4]
data_a[5] => altsyncram_qs41:auto_generated.data_a[5]
data_a[6] => altsyncram_qs41:auto_generated.data_a[6]
data_a[7] => altsyncram_qs41:auto_generated.data_a[7]
data_a[8] => altsyncram_qs41:auto_generated.data_a[8]
data_a[9] => altsyncram_qs41:auto_generated.data_a[9]
data_a[10] => altsyncram_qs41:auto_generated.data_a[10]
data_a[11] => altsyncram_qs41:auto_generated.data_a[11]
data_a[12] => altsyncram_qs41:auto_generated.data_a[12]
address_a[0] => altsyncram_qs41:auto_generated.address_a[0]
address_a[1] => altsyncram_qs41:auto_generated.address_a[1]
address_a[2] => altsyncram_qs41:auto_generated.address_a[2]
address_a[3] => altsyncram_qs41:auto_generated.address_a[3]
address_a[4] => altsyncram_qs41:auto_generated.address_a[4]
address_a[5] => altsyncram_qs41:auto_generated.address_a[5]
address_a[6] => altsyncram_qs41:auto_generated.address_a[6]
address_a[7] => altsyncram_qs41:auto_generated.address_a[7]
address_b[0] => altsyncram_qs41:auto_generated.address_b[0]
address_b[1] => altsyncram_qs41:auto_generated.address_b[1]
address_b[2] => altsyncram_qs41:auto_generated.address_b[2]
address_b[3] => altsyncram_qs41:auto_generated.address_b[3]
address_b[4] => altsyncram_qs41:auto_generated.address_b[4]
address_b[5] => altsyncram_qs41:auto_generated.address_b[5]
address_b[6] => altsyncram_qs41:auto_generated.address_b[6]
address_b[7] => altsyncram_qs41:auto_generated.address_b[7]
clock0 => altsyncram_qs41:auto_generated.clock0
clock1 => altsyncram_qs41:auto_generated.clock1
q_a[0] <= <UNC>
q_a[1] <= <UNC>
q_a[2] <= <UNC>
q_a[3] <= <UNC>
q_a[4] <= <UNC>
q_a[5] <= <UNC>
q_a[6] <= <UNC>
q_a[7] <= <UNC>
q_a[8] <= <UNC>
q_a[9] <= <UNC>
q_a[10] <= <UNC>
q_a[11] <= <UNC>
q_a[12] <= <UNC>
q_b[0] <= altsyncram_qs41:auto_generated.q_b[0]
q_b[1] <= altsyncram_qs41:auto_generated.q_b[1]
q_b[2] <= altsyncram_qs41:auto_generated.q_b[2]
q_b[3] <= altsyncram_qs41:auto_generated.q_b[3]
q_b[4] <= altsyncram_qs41:auto_generated.q_b[4]
q_b[5] <= altsyncram_qs41:auto_generated.q_b[5]
q_b[6] <= altsyncram_qs41:auto_generated.q_b[6]
q_b[7] <= altsyncram_qs41:auto_generated.q_b[7]
q_b[8] <= altsyncram_qs41:auto_generated.q_b[8]
q_b[9] <= altsyncram_qs41:auto_generated.q_b[9]
q_b[10] <= altsyncram_qs41:auto_generated.q_b[10]
q_b[11] <= altsyncram_qs41:auto_generated.q_b[11]
q_b[12] <= altsyncram_qs41:auto_generated.q_b[12]


|fir_top|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1