mux_kl7.tdf

logic lock 的vhdl源码

--lpm_mux DEVICE_FAMILY=Stratix LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 4.0 cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 8 
SUBDESIGN mux_kl7
( 
	data[15..0]	:	input;
	result[7..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[7..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data306w[1..0]	: WIRE;
	w_data320w[1..0]	: WIRE;
	w_data332w[1..0]	: WIRE;
	w_data344w[1..0]	: WIRE;
	w_data356w[1..0]	: WIRE;
	w_data368w[1..0]	: WIRE;
	w_data380w[1..0]	: WIRE;
	w_data392w[1..0]	: WIRE;
	w_result307w	: WIRE;
	w_result313w	: WIRE;
	w_result321w	: WIRE;
	w_result327w	: WIRE;
	w_result333w	: WIRE;
	w_result339w	: WIRE;
	w_result345w	: WIRE;
	w_result351w	: WIRE;
	w_result357w	: WIRE;
	w_result363w	: WIRE;
	w_result369w	: WIRE;
	w_result375w	: WIRE;
	w_result381w	: WIRE;
	w_result387w	: WIRE;
	w_result393w	: WIRE;
	w_result399w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result393w, w_result381w, w_result369w, w_result357w, w_result345w, w_result333w, w_result321w, w_result307w);
	sel_node[] = ( sel[0..0]);
	w_data306w[] = ( data[8..8], data[0..0]);
	w_data320w[] = ( data[9..9], data[1..1]);
	w_data332w[] = ( data[10..10], data[2..2]);
	w_data344w[] = ( data[11..11], data[3..3]);
	w_data356w[] = ( data[12..12], data[4..4]);
	w_data368w[] = ( data[13..13], data[5..5]);
	w_data380w[] = ( data[14..14], data[6..6]);
	w_data392w[] = ( data[15..15], data[7..7]);
	w_result307w = w_result313w;
	w_result313w = ((sel_node[] & w_data306w[1..1]) # ((! sel_node[]) & w_data306w[0..0]));
	w_result321w = w_result327w;
	w_result327w = ((sel_node[] & w_data320w[1..1]) # ((! sel_node[]) & w_data320w[0..0]));
	w_result333w = w_result339w;
	w_result339w = ((sel_node[] & w_data332w[1..1]) # ((! sel_node[]) & w_data332w[0..0]));
	w_result345w = w_result351w;
	w_result351w = ((sel_node[] & w_data344w[1..1]) # ((! sel_node[]) & w_data344w[0..0]));
	w_result357w = w_result363w;
	w_result363w = ((sel_node[] & w_data356w[1..1]) # ((! sel_node[]) & w_data356w[0..0]));
	w_result369w = w_result375w;
	w_result375w = ((sel_node[] & w_data368w[1..1]) # ((! sel_node[]) & w_data368w[0..0]));
	w_result381w = w_result387w;
	w_result387w = ((sel_node[] & w_data380w[1..1]) # ((! sel_node[]) & w_data380w[0..0]));
	w_result393w = w_result399w;
	w_result399w = ((sel_node[] & w_data392w[1..1]) # ((! sel_node[]) & w_data392w[0..0]));
END;
--VALID FILE