data_buffer.map.qmsg

logic lock 的vhdl源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 15 03:34:47 2004 " "Info: Processing started: Wed Dec 15 03:34:47 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off data_buffer -c data_buffer " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off data_buffer -c data_buffer" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "data_buffer.v 1 1 " "Info: Using design file data_buffer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 data_buffer " "Info: Found entity 1: data_buffer" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "data_buffer" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 37 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/eda/quartus/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "c:/eda/quartus/libraries/megafunctions/scfifo.tdf" "scfifo" "" { Text "c:/eda/quartus/libraries/megafunctions/scfifo.tdf" 239 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_39m.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/scfifo_39m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_39m " "Info: Found entity 1: scfifo_39m" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/scfifo_39m.tdf" "scfifo_39m" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/scfifo_39m.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_ihi.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/a_dpfifo_ihi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_ihi " "Info: Found entity 1: a_dpfifo_ihi" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_dpfifo_ihi.tdf" "a_dpfifo_ihi" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_dpfifo_ihi.tdf" 35 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_n4f.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/a_fefifo_n4f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_n4f " "Info: Found entity 1: a_fefifo_n4f" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" "a_fefifo_n4f" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_stratix " "Info: Found entity 1: alt_counter_stratix" {  } { { "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "alt_counter_stratix" "" { Text "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 282 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_btj.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/dpram_btj.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_btj " "Info: Found entity 1: dpram_btj" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/dpram_btj.tdf" "dpram_btj" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/dpram_btj.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_9kb1.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_9kb1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_9kb1 " "Info: Found entity 1: altsyncram_9kb1" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "altsyncram_9kb1" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 35 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_4r6.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/decode_4r6.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_4r6 " "Info: Found entity 1: decode_4r6" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/decode_4r6.tdf" "decode_4r6" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/decode_4r6.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_kl7.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/mux_kl7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_kl7 " "Info: Found entity 1: mux_kl7" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/mux_kl7.tdf" "mux_kl7" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/mux_kl7.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "102 " "Info: Implemented 102 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "65 " "Info: Implemented 65 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 15 03:34:53 2004 " "Info: Processing ended: Wed Dec 15 03:34:53 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}