data_buffer_hier_info

logic lock 的vhdl源码

address_b[10] => ram_block2a3.PORTBADDR10
address_b[10] => ram_block2a4.PORTBADDR10
address_b[10] => ram_block2a5.PORTBADDR10
address_b[10] => ram_block2a6.PORTBADDR10
address_b[10] => ram_block2a7.PORTBADDR10
address_b[10] => ram_block2a8.PORTBADDR10
address_b[10] => ram_block2a9.PORTBADDR10
address_b[10] => ram_block2a10.PORTBADDR10
address_b[10] => ram_block2a11.PORTBADDR10
address_b[10] => ram_block2a12.PORTBADDR10
address_b[10] => ram_block2a13.PORTBADDR10
address_b[10] => ram_block2a14.PORTBADDR10
address_b[10] => ram_block2a15.PORTBADDR10
address_b[11] => ram_block2a0.PORTBADDR11
address_b[11] => ram_block2a1.PORTBADDR11
address_b[11] => ram_block2a2.PORTBADDR11
address_b[11] => ram_block2a3.PORTBADDR11
address_b[11] => ram_block2a4.PORTBADDR11
address_b[11] => ram_block2a5.PORTBADDR11
address_b[11] => ram_block2a6.PORTBADDR11
address_b[11] => ram_block2a7.PORTBADDR11
address_b[11] => ram_block2a8.PORTBADDR11
address_b[11] => ram_block2a9.PORTBADDR11
address_b[11] => ram_block2a10.PORTBADDR11
address_b[11] => ram_block2a11.PORTBADDR11
address_b[11] => ram_block2a12.PORTBADDR11
address_b[11] => ram_block2a13.PORTBADDR11
address_b[11] => ram_block2a14.PORTBADDR11
address_b[11] => ram_block2a15.PORTBADDR11
address_b[12] => address_reg_b[0].DATAIN
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock0 => ram_block2a8.CLK0
clock0 => ram_block2a9.CLK0
clock0 => ram_block2a10.CLK0
clock0 => ram_block2a11.CLK0
clock0 => ram_block2a12.CLK0
clock0 => ram_block2a13.CLK0
clock0 => ram_block2a14.CLK0
clock0 => ram_block2a15.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clock1 => ram_block2a8.CLK1
clock1 => ram_block2a9.CLK1
clock1 => ram_block2a10.CLK1
clock1 => ram_block2a11.CLK1
clock1 => ram_block2a12.CLK1
clock1 => ram_block2a13.CLK1
clock1 => ram_block2a14.CLK1
clock1 => ram_block2a15.CLK1
clock1 => address_reg_b[0].CLK
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
clocken1 => ram_block2a8.ENA1
clocken1 => ram_block2a9.ENA1
clocken1 => ram_block2a10.ENA1
clocken1 => ram_block2a11.ENA1
clocken1 => ram_block2a12.ENA1
clocken1 => ram_block2a13.ENA1
clocken1 => ram_block2a14.ENA1
clocken1 => ram_block2a15.ENA1
clocken1 => address_reg_b[0].ENA
data_a[0] => ram_block2a0.PORTADATAIN
data_a[0] => ram_block2a8.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[1] => ram_block2a9.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[2] => ram_block2a10.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[3] => ram_block2a11.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[4] => ram_block2a12.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[5] => ram_block2a13.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[6] => ram_block2a14.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
data_a[7] => ram_block2a15.PORTADATAIN
q_b[0] <= mux_kl7:mux4.result[0]
q_b[1] <= mux_kl7:mux4.result[1]
q_b[2] <= mux_kl7:mux4.result[2]
q_b[3] <= mux_kl7:mux4.result[3]
q_b[4] <= mux_kl7:mux4.result[4]
q_b[5] <= mux_kl7:mux4.result[5]
q_b[6] <= mux_kl7:mux4.result[6]
q_b[7] <= mux_kl7:mux4.result[7]
wren_a => decode_4r6:decode3.enable


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|decode_4r6:decode3
data[0] => eq_node[1].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4
result[0] <= w_result313w.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= w_result327w.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= w_result339w.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= w_result351w.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= w_result363w.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= w_result375w.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= w_result387w.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= w_result399w.DB_MAX_OUTPUT_PORT_TYPE


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count
clock => alt_counter_stratix:wysi_counter.clock
cnt_en => alt_counter_stratix:wysi_counter.cnt_en
aclr => alt_counter_stratix:wysi_counter.aclr
sclr => alt_counter_stratix:wysi_counter.sclr
q[0] <= alt_counter_stratix:wysi_counter.q[0]
q[1] <= alt_counter_stratix:wysi_counter.q[1]
q[2] <= alt_counter_stratix:wysi_counter.q[2]
q[3] <= alt_counter_stratix:wysi_counter.q[3]
q[4] <= alt_counter_stratix:wysi_counter.q[4]
q[5] <= alt_counter_stratix:wysi_counter.q[5]
q[6] <= alt_counter_stratix:wysi_counter.q[6]
q[7] <= alt_counter_stratix:wysi_counter.q[7]
q[8] <= alt_counter_stratix:wysi_counter.q[8]
q[9] <= alt_counter_stratix:wysi_counter.q[9]
q[10] <= alt_counter_stratix:wysi_counter.q[10]
q[11] <= alt_counter_stratix:wysi_counter.q[11]
q[12] <= alt_counter_stratix:wysi_counter.q[12]
cout <= alt_counter_stratix:wysi_counter.cout


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter
clock => counter_cell[12].CLK
clock => counter_cell[11].CLK
clock => counter_cell[10].CLK
clock => counter_cell[9].CLK
clock => counter_cell[8].CLK
clock => counter_cell[7].CLK
clock => counter_cell[6].CLK
clock => counter_cell[5].CLK
clock => counter_cell[4].CLK
clock => counter_cell[3].CLK
clock => counter_cell[2].CLK
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
clk_en => counter_cell[12].ENA
clk_en => counter_cell[11].ENA
clk_en => counter_cell[10].ENA
clk_en => counter_cell[9].ENA
clk_en => counter_cell[8].ENA
clk_en => counter_cell[7].ENA
clk_en => counter_cell[6].ENA
clk_en => counter_cell[5].ENA
clk_en => counter_cell[4].ENA
clk_en => counter_cell[3].ENA
clk_en => counter_cell[2].ENA
clk_en => counter_cell[1].ENA
clk_en => counter_cell[0].ENA
cnt_en => counter_cell[12].DATAB
cnt_en => counter_cell[11].DATAB
cnt_en => counter_cell[10].DATAB
cnt_en => counter_cell[9].DATAB
cnt_en => counter_cell[8].DATAB
cnt_en => counter_cell[7].DATAB
cnt_en => counter_cell[6].DATAB
cnt_en => counter_cell[5].DATAB
cnt_en => counter_cell[4].DATAB
cnt_en => counter_cell[3].DATAB
cnt_en => counter_cell[2].DATAB
cnt_en => counter_cell[1].DATAB
cnt_en => counter_cell[0].DATAB
sclr => counter_cell[12].SCLR
sclr => counter_cell[11].SCLR
sclr => counter_cell[10].SCLR
sclr => counter_cell[9].SCLR
sclr => counter_cell[8].SCLR
sclr => counter_cell[7].SCLR
sclr => counter_cell[6].SCLR
sclr => counter_cell[5].SCLR
sclr => counter_cell[4].SCLR
sclr => counter_cell[3].SCLR
sclr => counter_cell[2].SCLR
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[12].ACLR
aclr => counter_cell[11].ACLR
aclr => counter_cell[10].ACLR
aclr => counter_cell[9].ACLR
aclr => counter_cell[8].ACLR
aclr => counter_cell[7].ACLR
aclr => counter_cell[6].ACLR
aclr => counter_cell[5].ACLR
aclr => counter_cell[4].ACLR
aclr => counter_cell[3].ACLR
aclr => counter_cell[2].ACLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
q[2] <= counter_cell[2].REGOUT
q[3] <= counter_cell[3].REGOUT
q[4] <= counter_cell[4].REGOUT
q[5] <= counter_cell[5].REGOUT
q[6] <= counter_cell[6].REGOUT
q[7] <= counter_cell[7].REGOUT
q[8] <= counter_cell[8].REGOUT
q[9] <= counter_cell[9].REGOUT
q[10] <= counter_cell[10].REGOUT
q[11] <= counter_cell[11].REGOUT
q[12] <= counter_cell[12].REGOUT
cout <= cout_bit.COMBOUT


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:wr_ptr
clock => alt_counter_stratix:wysi_counter.clock
cnt_en => alt_counter_stratix:wysi_counter.cnt_en
aclr => alt_counter_stratix:wysi_counter.aclr
sclr => alt_counter_stratix:wysi_counter.sclr
q[0] <= alt_counter_stratix:wysi_counter.q[0]
q[1] <= alt_counter_stratix:wysi_counter.q[1]
q[2] <= alt_counter_stratix:wysi_counter.q[2]
q[3] <= alt_counter_stratix:wysi_counter.q[3]
q[4] <= alt_counter_stratix:wysi_counter.q[4]
q[5] <= alt_counter_stratix:wysi_counter.q[5]
q[6] <= alt_counter_stratix:wysi_counter.q[6]
q[7] <= alt_counter_stratix:wysi_counter.q[7]
q[8] <= alt_counter_stratix:wysi_counter.q[8]
q[9] <= alt_counter_stratix:wysi_counter.q[9]
q[10] <= alt_counter_stratix:wysi_counter.q[10]
q[11] <= alt_counter_stratix:wysi_counter.q[11]
q[12] <= alt_counter_stratix:wysi_counter.q[12]
cout <= alt_counter_stratix:wysi_counter.cout


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter
clock => counter_cell[12].CLK
clock => counter_cell[11].CLK
clock => counter_cell[10].CLK
clock => counter_cell[9].CLK
clock => counter_cell[8].CLK
clock => counter_cell[7].CLK
clock => counter_cell[6].CLK
clock => counter_cell[5].CLK
clock => counter_cell[4].CLK
clock => counter_cell[3].CLK
clock => counter_cell[2].CLK
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
clk_en => counter_cell[12].ENA
clk_en => counter_cell[11].ENA
clk_en => counter_cell[10].ENA
clk_en => counter_cell[9].ENA
clk_en => counter_cell[8].ENA
clk_en => counter_cell[7].ENA
clk_en => counter_cell[6].ENA
clk_en => counter_cell[5].ENA
clk_en => counter_cell[4].ENA
clk_en => counter_cell[3].ENA
clk_en => counter_cell[2].ENA
clk_en => counter_cell[1].ENA
clk_en => counter_cell[0].ENA
cnt_en => counter_cell[12].DATAB
cnt_en => counter_cell[11].DATAB
cnt_en => counter_cell[10].DATAB
cnt_en => counter_cell[9].DATAB
cnt_en => counter_cell[8].DATAB
cnt_en => counter_cell[7].DATAB
cnt_en => counter_cell[6].DATAB
cnt_en => counter_cell[5].DATAB
cnt_en => counter_cell[4].DATAB
cnt_en => counter_cell[3].DATAB
cnt_en => counter_cell[2].DATAB
cnt_en => counter_cell[1].DATAB
cnt_en => counter_cell[0].DATAB
sclr => counter_cell[12].SCLR
sclr => counter_cell[11].SCLR
sclr => counter_cell[10].SCLR
sclr => counter_cell[9].SCLR
sclr => counter_cell[8].SCLR
sclr => counter_cell[7].SCLR
sclr => counter_cell[6].SCLR
sclr => counter_cell[5].SCLR
sclr => counter_cell[4].SCLR
sclr => counter_cell[3].SCLR
sclr => counter_cell[2].SCLR
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[12].ACLR
aclr => counter_cell[11].ACLR
aclr => counter_cell[10].ACLR
aclr => counter_cell[9].ACLR
aclr => counter_cell[8].ACLR
aclr => counter_cell[7].ACLR
aclr => counter_cell[6].ACLR
aclr => counter_cell[5].ACLR
aclr => counter_cell[4].ACLR
aclr => counter_cell[3].ACLR
aclr => counter_cell[2].ACLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
q[2] <= counter_cell[2].REGOUT
q[3] <= counter_cell[3].REGOUT
q[4] <= counter_cell[4].REGOUT
q[5] <= counter_cell[5].REGOUT
q[6] <= counter_cell[6].REGOUT
q[7] <= counter_cell[7].REGOUT
q[8] <= counter_cell[8].REGOUT
q[9] <= counter_cell[9].REGOUT
q[10] <= counter_cell[10].REGOUT
q[11] <= counter_cell[11].REGOUT
q[12] <= counter_cell[12].REGOUT
cout <= cout_bit.COMBOUT