data_buffer_hier_info

logic lock 的vhdl源码

|data_buffer
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wrreq => wrreq~0.IN1
rdreq => rdreq~0.IN1
clock => clock~0.IN1
q[0] <= scfifo:scfifo_component.q
q[1] <= scfifo:scfifo_component.q
q[2] <= scfifo:scfifo_component.q
q[3] <= scfifo:scfifo_component.q
q[4] <= scfifo:scfifo_component.q
q[5] <= scfifo:scfifo_component.q
q[6] <= scfifo:scfifo_component.q
q[7] <= scfifo:scfifo_component.q
full <= scfifo:scfifo_component.full
empty <= scfifo:scfifo_component.empty


|data_buffer|scfifo:scfifo_component
data[0] => scfifo_39m:auto_generated.data[0]
data[1] => scfifo_39m:auto_generated.data[1]
data[2] => scfifo_39m:auto_generated.data[2]
data[3] => scfifo_39m:auto_generated.data[3]
data[4] => scfifo_39m:auto_generated.data[4]
data[5] => scfifo_39m:auto_generated.data[5]
data[6] => scfifo_39m:auto_generated.data[6]
data[7] => scfifo_39m:auto_generated.data[7]
q[0] <= scfifo_39m:auto_generated.q[0]
q[1] <= scfifo_39m:auto_generated.q[1]
q[2] <= scfifo_39m:auto_generated.q[2]
q[3] <= scfifo_39m:auto_generated.q[3]
q[4] <= scfifo_39m:auto_generated.q[4]
q[5] <= scfifo_39m:auto_generated.q[5]
q[6] <= scfifo_39m:auto_generated.q[6]
q[7] <= scfifo_39m:auto_generated.q[7]
wrreq => scfifo_39m:auto_generated.wrreq
rdreq => scfifo_39m:auto_generated.rdreq
clock => scfifo_39m:auto_generated.clock
empty <= scfifo_39m:auto_generated.empty
full <= scfifo_39m:auto_generated.full
almost_full <= <UNC>
almost_empty <= <UNC>
usedw[0] <= <UNC>
usedw[1] <= <UNC>
usedw[2] <= <UNC>
usedw[3] <= <UNC>
usedw[4] <= <UNC>
usedw[5] <= <UNC>
usedw[6] <= <UNC>
usedw[7] <= <UNC>
usedw[8] <= <UNC>
usedw[9] <= <UNC>
usedw[10] <= <UNC>
usedw[11] <= <UNC>
usedw[12] <= <UNC>


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated
clock => a_dpfifo_ihi:dpfifo.clock
data[0] => a_dpfifo_ihi:dpfifo.data[0]
data[1] => a_dpfifo_ihi:dpfifo.data[1]
data[2] => a_dpfifo_ihi:dpfifo.data[2]
data[3] => a_dpfifo_ihi:dpfifo.data[3]
data[4] => a_dpfifo_ihi:dpfifo.data[4]
data[5] => a_dpfifo_ihi:dpfifo.data[5]
data[6] => a_dpfifo_ihi:dpfifo.data[6]
data[7] => a_dpfifo_ihi:dpfifo.data[7]
empty <= a_dpfifo_ihi:dpfifo.empty
full <= a_dpfifo_ihi:dpfifo.full
q[0] <= a_dpfifo_ihi:dpfifo.q[0]
q[1] <= a_dpfifo_ihi:dpfifo.q[1]
q[2] <= a_dpfifo_ihi:dpfifo.q[2]
q[3] <= a_dpfifo_ihi:dpfifo.q[3]
q[4] <= a_dpfifo_ihi:dpfifo.q[4]
q[5] <= a_dpfifo_ihi:dpfifo.q[5]
q[6] <= a_dpfifo_ihi:dpfifo.q[6]
q[7] <= a_dpfifo_ihi:dpfifo.q[7]
rdreq => a_dpfifo_ihi:dpfifo.rreq
usedw[0] <= a_dpfifo_ihi:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_ihi:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_ihi:dpfifo.usedw[2]
usedw[3] <= a_dpfifo_ihi:dpfifo.usedw[3]
usedw[4] <= a_dpfifo_ihi:dpfifo.usedw[4]
usedw[5] <= a_dpfifo_ihi:dpfifo.usedw[5]
usedw[6] <= a_dpfifo_ihi:dpfifo.usedw[6]
usedw[7] <= a_dpfifo_ihi:dpfifo.usedw[7]
usedw[8] <= a_dpfifo_ihi:dpfifo.usedw[8]
usedw[9] <= a_dpfifo_ihi:dpfifo.usedw[9]
usedw[10] <= a_dpfifo_ihi:dpfifo.usedw[10]
usedw[11] <= a_dpfifo_ihi:dpfifo.usedw[11]
usedw[12] <= a_dpfifo_ihi:dpfifo.usedw[12]
wrreq => a_dpfifo_ihi:dpfifo.wreq


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo
clock => a_fefifo_n4f:fifo_state.clock
clock => dpram_btj:FIFOram.inclock
clock => dpram_btj:FIFOram.outclock
clock => lpm_counter:rd_ptr_count.clock
clock => lpm_counter:wr_ptr.clock
data[0] => dpram_btj:FIFOram.data[0]
data[1] => dpram_btj:FIFOram.data[1]
data[2] => dpram_btj:FIFOram.data[2]
data[3] => dpram_btj:FIFOram.data[3]
data[4] => dpram_btj:FIFOram.data[4]
data[5] => dpram_btj:FIFOram.data[5]
data[6] => dpram_btj:FIFOram.data[6]
data[7] => dpram_btj:FIFOram.data[7]
empty <= a_fefifo_n4f:fifo_state.empty
full <= a_fefifo_n4f:fifo_state.full
q[0] <= dpram_btj:FIFOram.q[0]
q[1] <= dpram_btj:FIFOram.q[1]
q[2] <= dpram_btj:FIFOram.q[2]
q[3] <= dpram_btj:FIFOram.q[3]
q[4] <= dpram_btj:FIFOram.q[4]
q[5] <= dpram_btj:FIFOram.q[5]
q[6] <= dpram_btj:FIFOram.q[6]
q[7] <= dpram_btj:FIFOram.q[7]
rreq => a_fefifo_n4f:fifo_state.rreq
rreq => valid_rreq.IN0
sclr => a_fefifo_n4f:fifo_state.sclr
sclr => lpm_counter:rd_ptr_count.sclr
sclr => lpm_counter:wr_ptr.sclr
usedw[0] <= a_fefifo_n4f:fifo_state.usedw_out[0]
usedw[1] <= a_fefifo_n4f:fifo_state.usedw_out[1]
usedw[2] <= a_fefifo_n4f:fifo_state.usedw_out[2]
usedw[3] <= a_fefifo_n4f:fifo_state.usedw_out[3]
usedw[4] <= a_fefifo_n4f:fifo_state.usedw_out[4]
usedw[5] <= a_fefifo_n4f:fifo_state.usedw_out[5]
usedw[6] <= a_fefifo_n4f:fifo_state.usedw_out[6]
usedw[7] <= a_fefifo_n4f:fifo_state.usedw_out[7]
usedw[8] <= a_fefifo_n4f:fifo_state.usedw_out[8]
usedw[9] <= a_fefifo_n4f:fifo_state.usedw_out[9]
usedw[10] <= a_fefifo_n4f:fifo_state.usedw_out[10]
usedw[11] <= a_fefifo_n4f:fifo_state.usedw_out[11]
usedw[12] <= a_fefifo_n4f:fifo_state.usedw_out[12]
wreq => a_fefifo_n4f:fifo_state.wreq
wreq => valid_wreq.IN0


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state
aclr => lpm_counter:count_usedw.aclr
clock => lpm_counter:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
rreq => valid_rreq.IN0
sclr => lpm_counter:count_usedw.sclr
usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[6] <= usedw[6].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[7] <= usedw[7].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[8] <= usedw[8].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[9] <= usedw[9].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[10] <= usedw[10].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[11] <= usedw[11].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[12] <= usedw[12].DB_MAX_OUTPUT_PORT_TYPE
wreq => valid_wreq.IN0


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw
clock => alt_counter_stratix:wysi_counter.clock
cnt_en => alt_counter_stratix:wysi_counter.cnt_en
updown => alt_counter_stratix:wysi_counter.updown
aclr => alt_counter_stratix:wysi_counter.aclr
sclr => alt_counter_stratix:wysi_counter.sclr
q[0] <= alt_counter_stratix:wysi_counter.q[0]
q[1] <= alt_counter_stratix:wysi_counter.q[1]
q[2] <= alt_counter_stratix:wysi_counter.q[2]
q[3] <= alt_counter_stratix:wysi_counter.q[3]
q[4] <= alt_counter_stratix:wysi_counter.q[4]
q[5] <= alt_counter_stratix:wysi_counter.q[5]
q[6] <= alt_counter_stratix:wysi_counter.q[6]
q[7] <= alt_counter_stratix:wysi_counter.q[7]
q[8] <= alt_counter_stratix:wysi_counter.q[8]
q[9] <= alt_counter_stratix:wysi_counter.q[9]
q[10] <= alt_counter_stratix:wysi_counter.q[10]
q[11] <= alt_counter_stratix:wysi_counter.q[11]
q[12] <= alt_counter_stratix:wysi_counter.q[12]
cout <= alt_counter_stratix:wysi_counter.cout


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter
clock => counter_cell[12].CLK
clock => counter_cell[11].CLK
clock => counter_cell[10].CLK
clock => counter_cell[9].CLK
clock => counter_cell[8].CLK
clock => counter_cell[7].CLK
clock => counter_cell[6].CLK
clock => counter_cell[5].CLK
clock => counter_cell[4].CLK
clock => counter_cell[3].CLK
clock => counter_cell[2].CLK
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
updown => counter_cell[12].DATAB
updown => counter_cell[11].DATAB
updown => counter_cell[10].DATAB
updown => counter_cell[9].DATAB
updown => counter_cell[8].DATAB
updown => counter_cell[7].DATAB
updown => counter_cell[6].DATAB
updown => counter_cell[5].DATAB
updown => counter_cell[4].DATAB
updown => counter_cell[3].DATAB
updown => counter_cell[2].DATAB
updown => counter_cell[1].DATAB
updown => counter_cell[0].DATAB
updown => cout_bit.DATAA
sclr => counter_cell[12].SCLR
sclr => counter_cell[11].SCLR
sclr => counter_cell[10].SCLR
sclr => counter_cell[9].SCLR
sclr => counter_cell[8].SCLR
sclr => counter_cell[7].SCLR
sclr => counter_cell[6].SCLR
sclr => counter_cell[5].SCLR
sclr => counter_cell[4].SCLR
sclr => counter_cell[3].SCLR
sclr => counter_cell[2].SCLR
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[12].ACLR
aclr => counter_cell[11].ACLR
aclr => counter_cell[10].ACLR
aclr => counter_cell[9].ACLR
aclr => counter_cell[8].ACLR
aclr => counter_cell[7].ACLR
aclr => counter_cell[6].ACLR
aclr => counter_cell[5].ACLR
aclr => counter_cell[4].ACLR
aclr => counter_cell[3].ACLR
aclr => counter_cell[2].ACLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
q[2] <= counter_cell[2].REGOUT
q[3] <= counter_cell[3].REGOUT
q[4] <= counter_cell[4].REGOUT
q[5] <= counter_cell[5].REGOUT
q[6] <= counter_cell[6].REGOUT
q[7] <= counter_cell[7].REGOUT
q[8] <= counter_cell[8].REGOUT
q[9] <= counter_cell[9].REGOUT
q[10] <= counter_cell[10].REGOUT
q[11] <= counter_cell[11].REGOUT
q[12] <= counter_cell[12].REGOUT
cout <= cout_bit.COMBOUT


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram
data[0] => altsyncram_9kb1:altsyncram1.data_a[0]
data[1] => altsyncram_9kb1:altsyncram1.data_a[1]
data[2] => altsyncram_9kb1:altsyncram1.data_a[2]
data[3] => altsyncram_9kb1:altsyncram1.data_a[3]
data[4] => altsyncram_9kb1:altsyncram1.data_a[4]
data[5] => altsyncram_9kb1:altsyncram1.data_a[5]
data[6] => altsyncram_9kb1:altsyncram1.data_a[6]
data[7] => altsyncram_9kb1:altsyncram1.data_a[7]
inclock => altsyncram_9kb1:altsyncram1.clock0
outclock => altsyncram_9kb1:altsyncram1.clock1
outclocken => altsyncram_9kb1:altsyncram1.clocken1
q[0] <= altsyncram_9kb1:altsyncram1.q_b[0]
q[1] <= altsyncram_9kb1:altsyncram1.q_b[1]
q[2] <= altsyncram_9kb1:altsyncram1.q_b[2]
q[3] <= altsyncram_9kb1:altsyncram1.q_b[3]
q[4] <= altsyncram_9kb1:altsyncram1.q_b[4]
q[5] <= altsyncram_9kb1:altsyncram1.q_b[5]
q[6] <= altsyncram_9kb1:altsyncram1.q_b[6]
q[7] <= altsyncram_9kb1:altsyncram1.q_b[7]
rdaddress[0] => altsyncram_9kb1:altsyncram1.address_b[0]
rdaddress[1] => altsyncram_9kb1:altsyncram1.address_b[1]
rdaddress[2] => altsyncram_9kb1:altsyncram1.address_b[2]
rdaddress[3] => altsyncram_9kb1:altsyncram1.address_b[3]
rdaddress[4] => altsyncram_9kb1:altsyncram1.address_b[4]
rdaddress[5] => altsyncram_9kb1:altsyncram1.address_b[5]
rdaddress[6] => altsyncram_9kb1:altsyncram1.address_b[6]
rdaddress[7] => altsyncram_9kb1:altsyncram1.address_b[7]
rdaddress[8] => altsyncram_9kb1:altsyncram1.address_b[8]
rdaddress[9] => altsyncram_9kb1:altsyncram1.address_b[9]
rdaddress[10] => altsyncram_9kb1:altsyncram1.address_b[10]
rdaddress[11] => altsyncram_9kb1:altsyncram1.address_b[11]
rdaddress[12] => altsyncram_9kb1:altsyncram1.address_b[12]
wraddress[0] => altsyncram_9kb1:altsyncram1.address_a[0]
wraddress[1] => altsyncram_9kb1:altsyncram1.address_a[1]
wraddress[2] => altsyncram_9kb1:altsyncram1.address_a[2]
wraddress[3] => altsyncram_9kb1:altsyncram1.address_a[3]
wraddress[4] => altsyncram_9kb1:altsyncram1.address_a[4]
wraddress[5] => altsyncram_9kb1:altsyncram1.address_a[5]
wraddress[6] => altsyncram_9kb1:altsyncram1.address_a[6]
wraddress[7] => altsyncram_9kb1:altsyncram1.address_a[7]
wraddress[8] => altsyncram_9kb1:altsyncram1.address_a[8]
wraddress[9] => altsyncram_9kb1:altsyncram1.address_a[9]
wraddress[10] => altsyncram_9kb1:altsyncram1.address_a[10]
wraddress[11] => altsyncram_9kb1:altsyncram1.address_a[11]
wraddress[12] => altsyncram_9kb1:altsyncram1.address_a[12]
wren => altsyncram_9kb1:altsyncram1.wren_a


|data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[0] => ram_block2a8.PORTAADDR
address_a[0] => ram_block2a9.PORTAADDR
address_a[0] => ram_block2a10.PORTAADDR
address_a[0] => ram_block2a11.PORTAADDR
address_a[0] => ram_block2a12.PORTAADDR
address_a[0] => ram_block2a13.PORTAADDR
address_a[0] => ram_block2a14.PORTAADDR
address_a[0] => ram_block2a15.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1