data_buffer.vqm

logic lock 的vhdl源码

wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result351w~10 ;
wire \data[2]~combout ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a2 ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a10 ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result339w~10 ;
wire \data[1]~combout ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9 ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a1 ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result327w~10 ;
wire \data[0]~combout ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a0 ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a8 ;
wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result313w~10 ;
wire [12:0] \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q ;
wire [12:0] \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q ;
wire [0:0] \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|address_reg_b ;
wire [12:0] \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q ;

wire \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|__ALT_INV__b_non_empty ;

wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;

assign \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|__ALT_INV__b_non_empty  = ~ \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty ;

stratix_io \clock~I (
	.combout(\clock~combout ),
	.padio(clock));
defparam \clock~I .operation_mode = "input";
defparam \clock~I .ddio_mode = "none";
defparam \clock~I .input_register_mode = "none";
defparam \clock~I .output_register_mode = "none";
defparam \clock~I .oe_register_mode = "none";
defparam \clock~I .input_async_reset = "none";
defparam \clock~I .output_async_reset = "none";
defparam \clock~I .oe_async_reset = "none";
defparam \clock~I .input_sync_reset = "none";
defparam \clock~I .output_sync_reset = "none";
defparam \clock~I .oe_sync_reset = "none";
defparam \clock~I .input_power_up = "low";
defparam \clock~I .output_power_up = "low";
defparam \clock~I .oe_power_up = "low";

stratix_io \wrreq~I (
	.combout(\wrreq~combout ),
	.padio(wrreq));
defparam \wrreq~I .operation_mode = "input";
defparam \wrreq~I .ddio_mode = "none";
defparam \wrreq~I .input_register_mode = "none";
defparam \wrreq~I .output_register_mode = "none";
defparam \wrreq~I .oe_register_mode = "none";
defparam \wrreq~I .input_async_reset = "none";
defparam \wrreq~I .output_async_reset = "none";
defparam \wrreq~I .oe_async_reset = "none";
defparam \wrreq~I .input_sync_reset = "none";
defparam \wrreq~I .output_sync_reset = "none";
defparam \wrreq~I .oe_sync_reset = "none";
defparam \wrreq~I .input_power_up = "low";
defparam \wrreq~I .output_power_up = "low";
defparam \wrreq~I .oe_power_up = "low";

stratix_io \rdreq~I (
	.combout(\rdreq~combout ),
	.padio(rdreq));
defparam \rdreq~I .operation_mode = "input";
defparam \rdreq~I .ddio_mode = "none";
defparam \rdreq~I .input_register_mode = "none";
defparam \rdreq~I .output_register_mode = "none";
defparam \rdreq~I .oe_register_mode = "none";
defparam \rdreq~I .input_async_reset = "none";
defparam \rdreq~I .output_async_reset = "none";
defparam \rdreq~I .oe_async_reset = "none";
defparam \rdreq~I .input_sync_reset = "none";
defparam \rdreq~I .output_sync_reset = "none";
defparam \rdreq~I .oe_sync_reset = "none";
defparam \rdreq~I .input_power_up = "low";
defparam \rdreq~I .output_power_up = "low";
defparam \rdreq~I .oe_power_up = "low";

stratix_lcell \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0] (
	.clk(\clock~combout ),
	.dataa(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0] ),
	.datab(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|valid_wreq ),
	.aclr(gnd),
	.ena(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|_~68 ),
	.regout(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0] ),
	.cout(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT ));
defparam \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0] .operation_mode = "arithmetic";
defparam \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0] .synch_mode = "off";
defparam \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0] .register_cascade_mode = "off";
defparam \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0] .sum_lutc_input = "datac";
defparam \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0] .lut_mask = "5599";
defparam \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0] .output_mode = "reg_only";

stratix_lcell \scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[1] (
	.clk(\clock~combout ),
	.dataa(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1] ),
	.datab(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|valid_wreq ),
	.aclr(gnd),
	.ena(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|_~68 ),
	.cin(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT ),
	.regout(\scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1] ),