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📁 vhdl经典源代码——时钟设计
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<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_20(0) AND NOT XLXN_20(3) AND XLXN_19(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXN_19(1) AND NOT XLXN_19(2) AND XLXN_19(3)));
</td></tr><tr><td>
FTCPE_XLXN_202: FTCPE port map (XLXN_20(2),XLXN_20_T(2),XLXN_7,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_20_T(2) <= (XLXN_20(0) AND XLXN_20(1) AND XLXN_19(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXN_19(1) AND NOT XLXN_19(2) AND XLXN_19(3));
</td></tr><tr><td>
FTCPE_XLXN_203: FTCPE port map (XLXN_20(3),XLXN_20_T(3),XLXN_7,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_20_T(3) <= ((XLXN_20(0) AND XLXN_20(1) AND XLXN_20(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_19(0) AND NOT XLXN_19(1) AND NOT XLXN_19(2) AND XLXN_19(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_20(0) AND NOT XLXN_20(1) AND NOT XLXN_20(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_20(3) AND XLXN_19(0) AND NOT XLXN_19(1) AND NOT XLXN_19(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_19(3)));
</td></tr><tr><td>
FTCPE_XLXN_220: FTCPE port map (XLXN_22(0),'1',XLXN_9,NOT rst,'0',XLXN_22_CE(0));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_22_CE(0) <= (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_24(3));
</td></tr><tr><td>
FTCPE_XLXN_221: FTCPE port map (XLXN_22(1),XLXN_22_T(1),XLXN_9,NOT rst,'0',XLXN_22_CE(1));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_22_T(1) <= ((NOT XLXN_22(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_22(1) AND XLXN_22(2) AND NOT XLXN_22(3)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_22_CE(1) <= (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_24(3));
</td></tr><tr><td>
FTCPE_XLXN_222: FTCPE port map (XLXN_22(2),XLXN_22_T(2),XLXN_9,NOT rst,'0',XLXN_22_CE(2));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_22_T(2) <= ((XLXN_22(0) AND XLXN_22(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_22(0) AND XLXN_22(2) AND NOT XLXN_22(3)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_22_CE(2) <= (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_24(3));
</td></tr><tr><td>
FTCPE_XLXN_223: FTCPE port map (XLXN_22(3),XLXN_22_T(3),XLXN_9,NOT rst,'0',XLXN_22_CE(3));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_22_T(3) <= (XLXN_22(0) AND XLXN_22(1) AND XLXN_22(2));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_22_CE(3) <= (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_24(3));
</td></tr><tr><td>
FTCPE_XLXN_240: FTCPE port map (XLXN_24(0),'1',XLXN_9,NOT rst,'0');
</td></tr><tr><td>
FTCPE_XLXN_241: FTCPE port map (XLXN_24(1),XLXN_24_T(1),XLXN_9,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_24_T(1) <= ((NOT XLXN_24(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_24(1) AND NOT XLXN_24(2) AND XLXN_24(3)));
</td></tr><tr><td>
FTCPE_XLXN_242: FTCPE port map (XLXN_24(2),XLXN_24_T(2),XLXN_9,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_24_T(2) <= (XLXN_24(0) AND XLXN_24(1));
</td></tr><tr><td>
FTCPE_XLXN_243: FTCPE port map (XLXN_24(3),XLXN_24_T(3),XLXN_9,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_24_T(3) <= ((XLXN_24(0) AND XLXN_24(1) AND XLXN_24(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_24(3)));
</td></tr><tr><td>
FTCPE_XLXN_260: FTCPE port map (XLXN_26(0),'1',XLXN_6,NOT rst,'0');
</td></tr><tr><td>
FTCPE_XLXN_261: FTCPE port map (XLXN_26(1),XLXN_26_T(1),XLXN_6,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_26_T(1) <= ((NOT XLXN_26(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_26(1) AND NOT XLXN_26(2) AND XLXN_26(3)));
</td></tr><tr><td>
FTCPE_XLXN_262: FTCPE port map (XLXN_26(2),XLXN_26_T(2),XLXN_6,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_26_T(2) <= (XLXN_26(0) AND XLXN_26(1));
</td></tr><tr><td>
FTCPE_XLXN_263: FTCPE port map (XLXN_26(3),XLXN_26_T(3),XLXN_6,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_26_T(3) <= ((XLXN_26(0) AND XLXN_26(1) AND XLXN_26(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_26(3)));
</td></tr><tr><td>
FTCPE_XLXN_290: FTCPE port map (XLXN_29(0),'1',XLXN_6,NOT rst,'0',XLXN_29_CE(0));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_29_CE(0) <= (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_26(3));
</td></tr><tr><td>
FTCPE_XLXN_291: FTCPE port map (XLXN_29(1),XLXN_29_T(1),XLXN_6,NOT rst,'0',XLXN_29_CE(1));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_29_T(1) <= ((NOT XLXN_29(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_29(1) AND XLXN_29(2) AND NOT XLXN_29(3)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_29_CE(1) <= (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_26(3));
</td></tr><tr><td>
FTCPE_XLXN_292: FTCPE port map (XLXN_29(2),XLXN_29_T(2),XLXN_6,NOT rst,'0',XLXN_29_CE(2));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_29_T(2) <= ((XLXN_29(0) AND XLXN_29(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_29(0) AND XLXN_29(2) AND NOT XLXN_29(3)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_29_CE(2) <= (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_26(3));
</td></tr><tr><td>
FTCPE_XLXN_293: FTCPE port map (XLXN_29(3),XLXN_29_T(3),XLXN_6,NOT rst,'0',XLXN_29_CE(3));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_29_T(3) <= (XLXN_29(0) AND XLXN_29(1) AND XLXN_29(2));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_29_CE(3) <= (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_26(3));
</td></tr><tr><td>
FDCPE_XLXN_6: FDCPE port map (XLXN_6,XLXN_6_D,XLXN_9,'0','0',XLXN_6_CE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_6_D <= (XLXN_22(0) AND NOT XLXN_22(1) AND XLXN_22(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXN_22(3));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_6_CE <= (rst AND XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_24(3));
</td></tr><tr><td>
FDCPE_XLXN_7: FDCPE port map (XLXN_7,XLXN_7_D,XLXN_6,'0','0',XLXN_7_CE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_7_D <= (XLXN_29(0) AND NOT XLXN_29(1) AND XLXN_29(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXN_29(3));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_7_CE <= (rst AND XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_26(3));
</td></tr><tr><td>
FDCPE_XLXN_9: FDCPE port map (XLXN_9,XLXN_9_D,clk,'0','0',rst);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXN_9_D <= ((EXP10_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP11_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXI_3/cnt(24) AND NOT XLXI_3/cnt(25))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXI_3/cnt(20) AND NOT XLXI_3/cnt(22) AND NOT XLXI_3/cnt(23) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXI_3/cnt(25))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXI_3/cnt(21) AND NOT XLXI_3/cnt(22) AND NOT XLXI_3/cnt(23) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXI_3/cnt(25)));
</td></tr><tr><td>
</td></tr><tr><td>
dataout(0) <= '1';
</td></tr><tr><td>
</td></tr><tr><td>
dataout(1) <= ((en_5_OBUF.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(2) AND NOT XLXN_13(3) AND XLXN_13(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_13(0)));
</td></tr><tr><td>
</td></tr><tr><td>
dataout(2) <= ((XLXN_13(2) AND XLXN_13(3) AND XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND XLXN_13(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(3) AND XLXN_13(1) AND XLXN_13(0)));
</td></tr><tr><td>
</td></tr><tr><td>
dataout(3) <= ((NOT XLXN_13(3) AND XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(2) AND XLXN_13(1) AND XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(2) AND NOT XLXN_13(1) AND XLXN_13(0)));
</td></tr><tr><td>
</td></tr><tr><td>
dataout(4) <= ((XLXN_13(2) AND XLXN_13(1) AND XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(2) AND NOT XLXN_13(1) AND XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(2) AND XLXN_13(3) AND XLXN_13(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXN_13(0)));
</td></tr><tr><td>
</td></tr><tr><td>
dataout(5) <= ((XLXN_13(2) AND XLXN_13(3) AND XLXN_13(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(2) AND XLXN_13(3) AND NOT XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND XLXN_13(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXN_13(0)));
</td></tr><tr><td>
</td></tr><tr><td>
dataout(6) <= ((XLXI_1/cnt(5).EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(2) AND XLXN_13(3) AND NOT XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(3) AND XLXN_13(1) AND XLXN_13(0)));
</td></tr><tr><td>
</td></tr><tr><td>
dataout(7) <= ((XLXN_13(2) AND XLXN_13(3) AND XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(3) AND XLXN_13(1) AND XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXN_13(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXN_13(0)));
</td></tr><tr><td>
FDCPE_en0: FDCPE port map (en(0),en_D(0),XLXN_10,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;en_D(0) <= (XLXI_6/cnt(0) AND XLXI_6/cnt(1) AND XLXI_6/cnt(2));
</td></tr><tr><td>
FDCPE_en1: FDCPE port map (en(1),en_D(1),XLXN_10,'0',NOT rst);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;en_D(1) <= (NOT XLXI_6/cnt(0) AND NOT XLXI_6/cnt(1) AND NOT XLXI_6/cnt(2));
</td></tr><tr><td>
FDCPE_en2: FDCPE port map (en(2),en_D(2),XLXN_10,'0',NOT rst);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;en_D(2) <= (XLXI_6/cnt(0) AND NOT XLXI_6/cnt(1) AND NOT XLXI_6/cnt(2));
</td></tr><tr><td>
FDCPE_en3: FDCPE port map (en(3),en_D(3),XLXN_10,'0',NOT rst);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;en_D(3) <= (NOT XLXI_6/cnt(0) AND XLXI_6/cnt(1) AND NOT XLXI_6/cnt(2));
</td></tr><tr><td>
FDCPE_en4: FDCPE port map (en(4),en_D(4),XLXN_10,'0',NOT rst);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;en_D(4) <= (XLXI_6/cnt(0) AND XLXI_6/cnt(1) AND NOT XLXI_6/cnt(2));
</td></tr><tr><td>
FDCPE_en5: FDCPE port map (en(5),en_D(5),XLXN_10,'0',NOT rst);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;en_D(5) <= (NOT XLXI_6/cnt(0) AND NOT XLXI_6/cnt(1) AND XLXI_6/cnt(2));
</td></tr><tr><td>
FDCPE_en6: FDCPE port map (en(6),en_D(6),XLXN_10,'0',NOT rst);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;en_D(6) <= (XLXI_6/cnt(0) AND NOT XLXI_6/cnt(1) AND XLXI_6/cnt(2));
</td></tr><tr><td>
FDCPE_en7: FDCPE port map (en(7),en_D(7),XLXN_10,'0',NOT rst);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;en_D(7) <= (NOT XLXI_6/cnt(0) AND XLXI_6/cnt(1) AND XLXI_6/cnt(2));
</td></tr><tr><td>
Register Legend:
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDCP  (Q,D,G,CLR,PRE); 
</td></tr><tr><td>
</td></tr>
</table>
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