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📄 defeqns.htm

📁 vhdl经典源代码——时钟设计
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<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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FTCPE_XLXI_1/cnt0: FTCPE port map (XLXI_1/cnt(0),'1',clk,NOT rst,'0');
</td></tr><tr><td>
FTCPE_XLXI_1/cnt1: FTCPE port map (XLXI_1/cnt(1),XLXI_1/cnt(0),clk,NOT rst,'0');
</td></tr><tr><td>
FTCPE_XLXI_1/cnt2: FTCPE port map (XLXI_1/cnt(2),XLXI_1/cnt_T(2),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(2) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(1));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt3: FTCPE port map (XLXI_1/cnt(3),XLXI_1/cnt(4).EXP,clk,NOT rst,'0');
</td></tr><tr><td>
FTCPE_XLXI_1/cnt4: FTCPE port map (XLXI_1/cnt(4),XLXI_1/cnt_T(4),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(4) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt5: FTCPE port map (XLXI_1/cnt(5),XLXI_1/cnt_T(5),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(5) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt6: FTCPE port map (XLXI_1/cnt(6),XLXI_1/cnt_T(6),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(6) <= ((NOT XLXI_1/cnt(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXI_1/cnt(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXI_1/cnt(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_1/cnt(10).EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (dataout_6_OBUF.EXP));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt7: FTCPE port map (XLXI_1/cnt(7),XLXI_1/cnt_T(7),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(7) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt8: FTCPE port map (XLXI_1/cnt(8),XLXI_1/cnt_T(8),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(8) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt9: FTCPE port map (XLXI_1/cnt(9),XLXI_1/cnt_T(9),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(9) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(7) AND XLXI_1/cnt(8));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt10: FTCPE port map (XLXI_1/cnt(10),XLXI_1/cnt_T(10),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(10) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND XLXI_1/cnt(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND NOT XLXI_1/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt11: FTCPE port map (XLXI_1/cnt(11),XLXI_1/cnt_T(11),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(11) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(2) AND XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(6) AND XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND XLXI_1/cnt(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND NOT XLXI_1/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt12: FTCPE port map (XLXI_1/cnt(12),XLXI_1/cnt_T(12),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(12) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND NOT XLXI_1/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt13: FTCPE port map (XLXI_1/cnt(13),XLXI_1/cnt_T(13),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(13) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(12) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND XLXI_1/cnt(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND XLXI_1/cnt(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(8) AND XLXI_1/cnt(9));
</td></tr><tr><td>
FTCPE_XLXI_1/cnt14: FTCPE port map (XLXI_1/cnt(14),XLXI_1/cnt_T(14),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_1/cnt_T(14) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(12) AND XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND XLXI_1/cnt(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND NOT XLXI_1/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt0: FTCPE port map (XLXI_3/cnt(0),'1',clk,NOT rst,'0');
</td></tr><tr><td>
FTCPE_XLXI_3/cnt1: FTCPE port map (XLXI_3/cnt(1),XLXI_3/cnt(0),clk,NOT rst,'0');
</td></tr><tr><td>
FTCPE_XLXI_3/cnt2: FTCPE port map (XLXI_3/cnt(2),XLXI_3/cnt_T(2),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(2) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt3: FTCPE port map (XLXI_3/cnt(3),XLXI_3/cnt_T(3),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(3) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt4: FTCPE port map (XLXI_3/cnt(4),XLXI_3/cnt_T(4),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(4) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(3));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt5: FTCPE port map (XLXI_3/cnt(5),XLXI_3/cnt_T(5),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(5) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(3) AND XLXI_3/cnt(4));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt6: FTCPE port map (XLXI_3/cnt(6),XLXI_3/cnt_T(6),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(6) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt7: FTCPE port map (XLXI_3/cnt(7),XLXI_3/cnt_T(7),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(7) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt8: FTCPE port map (XLXI_3/cnt(8),XLXI_3/cnt_T(8),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(8) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(7));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt9: FTCPE port map (XLXI_3/cnt(9),XLXI_3/cnt_T(9),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(9) <= ((NOT XLXI_3/cnt(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXI_3/cnt(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT XLXI_3/cnt(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_3/cnt(3).EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP12_.EXP));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt10: FTCPE port map (XLXI_3/cnt(10),XLXI_3/cnt_T(10),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(10) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(7) AND XLXI_3/cnt(8) AND XLXI_3/cnt(9));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt11: FTCPE port map (XLXI_3/cnt(11),XLXI_3/cnt_T(11),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(11) <= ((XLXI_3/cnt(12).EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_3/cnt(0) AND XLXI_3/cnt(10) AND XLXI_3/cnt(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(2) AND XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(6) AND XLXI_3/cnt(7) AND XLXI_3/cnt(8) AND XLXI_3/cnt(9)));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt12: FTCPE port map (XLXI_3/cnt(12),XLXI_3/cnt_T(12),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(12) <= ((XLXI_3/cnt(0) AND XLXI_3/cnt(10) AND XLXI_3/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND XLXI_3/cnt(7) AND XLXI_3/cnt(8) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_3/cnt(0) AND NOT XLXI_3/cnt(10) AND XLXI_3/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(12) AND NOT XLXI_3/cnt(13) AND XLXI_3/cnt(14) AND NOT XLXI_3/cnt(15) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXI_3/cnt(16) AND XLXI_3/cnt(17) AND NOT XLXI_3/cnt(18) AND NOT XLXI_3/cnt(19) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(1) AND NOT XLXI_3/cnt(20) AND XLXI_3/cnt(21) AND XLXI_3/cnt(22) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXI_3/cnt(23) AND NOT XLXI_3/cnt(24) AND XLXI_3/cnt(2) AND XLXI_3/cnt(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND XLXI_3/cnt(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(8) AND NOT XLXI_3/cnt(9) AND XLXI_3/cnt(25)));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt13: FTCPE port map (XLXI_3/cnt(13),XLXI_3/cnt_T(13),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(13) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(10) AND XLXI_3/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(12) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND XLXI_3/cnt(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND XLXI_3/cnt(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(8) AND XLXI_3/cnt(9));
</td></tr><tr><td>
FTCPE_XLXI_3/cnt14: FTCPE port map (XLXI_3/cnt(14),XLXI_3/cnt_T(14),clk,NOT rst,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;XLXI_3/cnt_T(14) <= ((XLXI_3/cnt(0) AND XLXI_3/cnt(10) AND XLXI_3/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(12) AND XLXI_3/cnt(13) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(7) AND XLXI_3/cnt(8) AND XLXI_3/cnt(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (XLXI_3/cnt(0) AND NOT XLXI_3/cnt(10) AND XLXI_3/cnt(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(12) AND NOT XLXI_3/cnt(13) AND XLXI_3/cnt(14) AND NOT XLXI_3/cnt(15) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXI_3/cnt(16) AND XLXI_3/cnt(17) AND NOT XLXI_3/cnt(18) AND NOT XLXI_3/cnt(19) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(1) AND NOT XLXI_3/cnt(20) AND XLXI_3/cnt(21) AND XLXI_3/cnt(22) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT XLXI_3/cnt(23) AND NOT XLXI_3/cnt(24) AND XLXI_3/cnt(2) AND XLXI_3/cnt(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND XLXI_3/cnt(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XLXI_3/cnt(8) AND NOT XLXI_3/cnt(9) AND XLXI_3/cnt(25)));

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