📄 clock.rpt
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XLXN_19(0) AND NOT XLXN_19(1) AND NOT XLXN_19(2) AND XLXN_19(3))
OR (XLXN_20(0) AND NOT XLXN_20(1) AND NOT XLXN_20(2) AND
XLXN_20(3) AND XLXN_19(0) AND NOT XLXN_19(1) AND NOT XLXN_19(2) AND
XLXN_19(3)));
FTCPE_XLXN_220: FTCPE port map (XLXN_22(0),'1',XLXN_9,NOT rst,'0',XLXN_22_CE(0));
XLXN_22_CE(0) <= (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND
XLXN_24(3));
FTCPE_XLXN_221: FTCPE port map (XLXN_22(1),XLXN_22_T(1),XLXN_9,NOT rst,'0',XLXN_22_CE(1));
XLXN_22_T(1) <= ((NOT XLXN_22(0))
OR (NOT XLXN_22(1) AND XLXN_22(2) AND NOT XLXN_22(3)));
XLXN_22_CE(1) <= (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND
XLXN_24(3));
FTCPE_XLXN_222: FTCPE port map (XLXN_22(2),XLXN_22_T(2),XLXN_9,NOT rst,'0',XLXN_22_CE(2));
XLXN_22_T(2) <= ((XLXN_22(0) AND XLXN_22(1))
OR (XLXN_22(0) AND XLXN_22(2) AND NOT XLXN_22(3)));
XLXN_22_CE(2) <= (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND
XLXN_24(3));
FTCPE_XLXN_223: FTCPE port map (XLXN_22(3),XLXN_22_T(3),XLXN_9,NOT rst,'0',XLXN_22_CE(3));
XLXN_22_T(3) <= (XLXN_22(0) AND XLXN_22(1) AND XLXN_22(2));
XLXN_22_CE(3) <= (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND
XLXN_24(3));
FTCPE_XLXN_240: FTCPE port map (XLXN_24(0),'1',XLXN_9,NOT rst,'0');
FTCPE_XLXN_241: FTCPE port map (XLXN_24(1),XLXN_24_T(1),XLXN_9,NOT rst,'0');
XLXN_24_T(1) <= ((NOT XLXN_24(0))
OR (NOT XLXN_24(1) AND NOT XLXN_24(2) AND XLXN_24(3)));
FTCPE_XLXN_242: FTCPE port map (XLXN_24(2),XLXN_24_T(2),XLXN_9,NOT rst,'0');
XLXN_24_T(2) <= (XLXN_24(0) AND XLXN_24(1));
FTCPE_XLXN_243: FTCPE port map (XLXN_24(3),XLXN_24_T(3),XLXN_9,NOT rst,'0');
XLXN_24_T(3) <= ((XLXN_24(0) AND XLXN_24(1) AND XLXN_24(2))
OR (XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND
XLXN_24(3)));
FTCPE_XLXN_260: FTCPE port map (XLXN_26(0),'1',XLXN_6,NOT rst,'0');
FTCPE_XLXN_261: FTCPE port map (XLXN_26(1),XLXN_26_T(1),XLXN_6,NOT rst,'0');
XLXN_26_T(1) <= ((NOT XLXN_26(0))
OR (NOT XLXN_26(1) AND NOT XLXN_26(2) AND XLXN_26(3)));
FTCPE_XLXN_262: FTCPE port map (XLXN_26(2),XLXN_26_T(2),XLXN_6,NOT rst,'0');
XLXN_26_T(2) <= (XLXN_26(0) AND XLXN_26(1));
FTCPE_XLXN_263: FTCPE port map (XLXN_26(3),XLXN_26_T(3),XLXN_6,NOT rst,'0');
XLXN_26_T(3) <= ((XLXN_26(0) AND XLXN_26(1) AND XLXN_26(2))
OR (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND
XLXN_26(3)));
FTCPE_XLXN_290: FTCPE port map (XLXN_29(0),'1',XLXN_6,NOT rst,'0',XLXN_29_CE(0));
XLXN_29_CE(0) <= (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND
XLXN_26(3));
FTCPE_XLXN_291: FTCPE port map (XLXN_29(1),XLXN_29_T(1),XLXN_6,NOT rst,'0',XLXN_29_CE(1));
XLXN_29_T(1) <= ((NOT XLXN_29(0))
OR (NOT XLXN_29(1) AND XLXN_29(2) AND NOT XLXN_29(3)));
XLXN_29_CE(1) <= (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND
XLXN_26(3));
FTCPE_XLXN_292: FTCPE port map (XLXN_29(2),XLXN_29_T(2),XLXN_6,NOT rst,'0',XLXN_29_CE(2));
XLXN_29_T(2) <= ((XLXN_29(0) AND XLXN_29(1))
OR (XLXN_29(0) AND XLXN_29(2) AND NOT XLXN_29(3)));
XLXN_29_CE(2) <= (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND
XLXN_26(3));
FTCPE_XLXN_293: FTCPE port map (XLXN_29(3),XLXN_29_T(3),XLXN_6,NOT rst,'0',XLXN_29_CE(3));
XLXN_29_T(3) <= (XLXN_29(0) AND XLXN_29(1) AND XLXN_29(2));
XLXN_29_CE(3) <= (XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND
XLXN_26(3));
FDCPE_XLXN_6: FDCPE port map (XLXN_6,XLXN_6_D,XLXN_9,'0','0',XLXN_6_CE);
XLXN_6_D <= (XLXN_22(0) AND NOT XLXN_22(1) AND XLXN_22(2) AND
NOT XLXN_22(3));
XLXN_6_CE <= (rst AND XLXN_24(0) AND NOT XLXN_24(1) AND NOT XLXN_24(2) AND
XLXN_24(3));
FDCPE_XLXN_7: FDCPE port map (XLXN_7,XLXN_7_D,XLXN_6,'0','0',XLXN_7_CE);
XLXN_7_D <= (XLXN_29(0) AND NOT XLXN_29(1) AND XLXN_29(2) AND
NOT XLXN_29(3));
XLXN_7_CE <= (rst AND XLXN_26(0) AND NOT XLXN_26(1) AND NOT XLXN_26(2) AND
XLXN_26(3));
FDCPE_XLXN_9: FDCPE port map (XLXN_9,XLXN_9_D,clk,'0','0',rst);
XLXN_9_D <= ((EXP10_.EXP)
OR (EXP11_.EXP)
OR (NOT XLXI_3/cnt(24) AND NOT XLXI_3/cnt(25))
OR (NOT XLXI_3/cnt(20) AND NOT XLXI_3/cnt(22) AND NOT XLXI_3/cnt(23) AND
NOT XLXI_3/cnt(25))
OR (NOT XLXI_3/cnt(21) AND NOT XLXI_3/cnt(22) AND NOT XLXI_3/cnt(23) AND
NOT XLXI_3/cnt(25)));
dataout(0) <= '1';
dataout(1) <= ((en_5_OBUF.EXP)
OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1))
OR (XLXN_13(2) AND NOT XLXN_13(3) AND XLXN_13(1) AND
XLXN_13(0)));
dataout(2) <= ((XLXN_13(2) AND XLXN_13(3) AND XLXN_13(0))
OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND XLXN_13(1))
OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND XLXN_13(0))
OR (NOT XLXN_13(3) AND XLXN_13(1) AND XLXN_13(0)));
dataout(3) <= ((NOT XLXN_13(3) AND XLXN_13(0))
OR (XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1))
OR (XLXN_13(2) AND XLXN_13(1) AND XLXN_13(0))
OR (NOT XLXN_13(2) AND NOT XLXN_13(1) AND XLXN_13(0)));
dataout(4) <= ((XLXN_13(2) AND XLXN_13(1) AND XLXN_13(0))
OR (NOT XLXN_13(2) AND NOT XLXN_13(1) AND XLXN_13(0))
OR (XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1) AND
NOT XLXN_13(0))
OR (NOT XLXN_13(2) AND XLXN_13(3) AND XLXN_13(1) AND
NOT XLXN_13(0)));
dataout(5) <= ((XLXN_13(2) AND XLXN_13(3) AND XLXN_13(1))
OR (XLXN_13(2) AND XLXN_13(3) AND NOT XLXN_13(0))
OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND XLXN_13(1) AND
NOT XLXN_13(0)));
dataout(6) <= ((XLXI_1/cnt(5).EXP)
OR (XLXN_13(2) AND XLXN_13(3) AND NOT XLXN_13(0))
OR (XLXN_13(3) AND XLXN_13(1) AND XLXN_13(0)));
dataout(7) <= ((XLXN_13(2) AND XLXN_13(3) AND XLXN_13(0))
OR (XLXN_13(3) AND XLXN_13(1) AND XLXN_13(0))
OR (XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1) AND
NOT XLXN_13(0))
OR (NOT XLXN_13(2) AND NOT XLXN_13(3) AND NOT XLXN_13(1) AND
XLXN_13(0)));
FDCPE_en0: FDCPE port map (en(0),en_D(0),XLXN_10,NOT rst,'0');
en_D(0) <= (XLXI_6/cnt(0) AND XLXI_6/cnt(1) AND XLXI_6/cnt(2));
FDCPE_en1: FDCPE port map (en(1),en_D(1),XLXN_10,'0',NOT rst);
en_D(1) <= (NOT XLXI_6/cnt(0) AND NOT XLXI_6/cnt(1) AND NOT XLXI_6/cnt(2));
FDCPE_en2: FDCPE port map (en(2),en_D(2),XLXN_10,'0',NOT rst);
en_D(2) <= (XLXI_6/cnt(0) AND NOT XLXI_6/cnt(1) AND NOT XLXI_6/cnt(2));
FDCPE_en3: FDCPE port map (en(3),en_D(3),XLXN_10,'0',NOT rst);
en_D(3) <= (NOT XLXI_6/cnt(0) AND XLXI_6/cnt(1) AND NOT XLXI_6/cnt(2));
FDCPE_en4: FDCPE port map (en(4),en_D(4),XLXN_10,'0',NOT rst);
en_D(4) <= (XLXI_6/cnt(0) AND XLXI_6/cnt(1) AND NOT XLXI_6/cnt(2));
FDCPE_en5: FDCPE port map (en(5),en_D(5),XLXN_10,'0',NOT rst);
en_D(5) <= (NOT XLXI_6/cnt(0) AND NOT XLXI_6/cnt(1) AND XLXI_6/cnt(2));
FDCPE_en6: FDCPE port map (en(6),en_D(6),XLXN_10,'0',NOT rst);
en_D(6) <= (XLXI_6/cnt(0) AND NOT XLXI_6/cnt(1) AND XLXI_6/cnt(2));
FDCPE_en7: FDCPE port map (en(7),en_D(7),XLXN_10,'0',NOT rst);
en_D(7) <= (NOT XLXI_6/cnt(0) AND XLXI_6/cnt(1) AND XLXI_6/cnt(2));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 KPR 74 KPR
3 KPR 75 KPR
4 KPR 76 KPR
5 KPR 77 KPR
6 KPR 78 KPR
7 KPR 79 KPR
8 VCC 80 KPR
9 KPR 81 KPR
10 KPR 82 KPR
11 KPR 83 KPR
12 KPR 84 VCC
13 KPR 85 KPR
14 KPR 86 KPR
15 KPR 87 KPR
16 KPR 88 KPR
17 KPR 89 GND
18 GND 90 GND
19 KPR 91 KPR
20 KPR 92 KPR
21 KPR 93 KPR
22 KPR 94 KPR
23 KPR 95 KPR
24 KPR 96 KPR
25 KPR 97 KPR
26 KPR 98 KPR
27 KPR 99 GND
28 KPR 100 KPR
29 GND 101 KPR
30 KPR 102 KPR
31 KPR 103 KPR
32 KPR 104 KPR
33 KPR 105 KPR
34 KPR 106 dataout<7>
35 KPR 107 dataout<6>
36 GND 108 GND
37 VCC 109 VCC
38 KPR 110 KPR
39 KPR 111 dataout<5>
40 KPR 112 KPR
41 KPR 113 dataout<4>
42 VCC 114 GND
43 KPR 115 dataout<3>
44 KPR 116 dataout<2>
45 KPR 117 KPR
46 KPR 118 dataout<1>
47 GND 119 dataout<0>
48 KPR 120 en<4>
49 KPR 121 KPR
50 KPR 122 TDO
51 KPR 123 GND
52 KPR 124 en<3>
53 KPR 125 en<2>
54 KPR
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