📄 clock.rpt
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XLXI_3/cnt<13> XXXX.....XXXXXXXXX........XX............ 15
en<2> ..................XXXX.....X............ 5
XLXI_3/cnt<10> X........XXXXXXXXX........XX............ 12
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 71 I/O I
(unused) 0 0 0 5 FB7_3 75 I/O
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 74 I/O
(unused) 0 0 0 5 FB7_6 76 I/O
(unused) 0 0 0 5 FB7_7 77 I/O
(unused) 0 0 0 5 FB7_8 78 I/O
(unused) 0 0 0 5 FB7_9 80 I/O
(unused) 0 0 0 5 FB7_10 79 I/O
(unused) 0 0 0 5 FB7_11 82 I/O
(unused) 0 0 0 5 FB7_12 85 I/O
(unused) 0 0 0 5 FB7_13 81 I/O
(unused) 0 0 0 5 FB7_14 86 I/O
(unused) 0 0 0 5 FB7_15 87 I/O
(unused) 0 0 0 5 FB7_16 83 I/O
(unused) 0 0 0 5 FB7_17 88 I/O
(unused) 0 0 0 5 FB7_18 (b)
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
XLXI_1/cnt<9> 3 0 0 2 FB8_1 (b) (b)
XLXI_1/cnt<4> 3 0 \/1 1 FB8_2 91 I/O (b)
XLXI_1/cnt<3> 3 1<- \/3 0 FB8_3 95 I/O (b)
XLXN_10 15 10<- 0 0 FB8_4 97 I/O (b)
(unused) 0 0 /\5 0 FB8_5 92 I/O (b)
XLXI_1/cnt<13> 3 0 /\2 0 FB8_6 93 I/O (b)
XLXN_26<3> 4 0 0 1 FB8_7 (b) (b)
XLXN_26<1> 4 0 0 1 FB8_8 94 I/O (b)
XLXI_1/cnt<8> 4 0 0 1 FB8_9 96 I/O (b)
XLXI_1/cnt<7> 4 0 0 1 FB8_10 101 I/O (b)
XLXI_1/cnt<14> 4 0 0 1 FB8_11 98 I/O (b)
XLXI_1/cnt<12> 4 0 0 1 FB8_12 100 I/O (b)
XLXI_1/cnt<11> 4 0 0 1 FB8_13 103 I/O (b)
XLXI_1/cnt<10> 4 0 \/1 0 FB8_14 102 I/O (b)
XLXI_1/cnt<6> 9 4<- 0 0 FB8_15 104 I/O (b)
dataout<6> 4 2<- /\3 0 FB8_16 107 I/O O
XLXI_1/cnt<5> 3 0 /\2 0 FB8_17 105 I/O (b)
XLXN_26<0> 2 0 0 3 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: XLXI_1/cnt<0> 10: XLXI_1/cnt<4> 19: XLXN_13<3>
2: XLXI_1/cnt<10> 11: XLXI_1/cnt<5> 20: XLXN_26<0>
3: XLXI_1/cnt<11> 12: XLXI_1/cnt<6> 21: XLXN_26<1>
4: XLXI_1/cnt<12> 13: XLXI_1/cnt<7> 22: XLXN_26<2>
5: XLXI_1/cnt<13> 14: XLXI_1/cnt<8> 23: XLXN_26<3>
6: XLXI_1/cnt<14> 15: XLXI_1/cnt<9> 24: XLXN_6
7: XLXI_1/cnt<1> 16: XLXN_13<0> 25: clk
8: XLXI_1/cnt<2> 17: XLXN_13<1> 26: rst
9: XLXI_1/cnt<3> 18: XLXN_13<2>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
XLXI_1/cnt<9> X.....XXXXXXXX..........XX.............. 11
XLXI_1/cnt<4> X.....XXX...............XX.............. 6
XLXI_1/cnt<3> X.....XX................XX.............. 5
XLXN_10 XXXXXXXXXXXXXXX.........XX.............. 17
XLXI_1/cnt<13> XXXX..XXXXXXXXX.........XX.............. 15
XLXN_26<3> ...................XXXXX.X.............. 6
XLXN_26<1> ...................XXXXX.X.............. 6
XLXI_1/cnt<8> XXXXXXXXXXXXXXX.........XX.............. 17
XLXI_1/cnt<7> XXXXXXXXXXXXXXX.........XX.............. 17
XLXI_1/cnt<14> XXXXXXXXXXXXXXX.........XX.............. 17
XLXI_1/cnt<12> XXXXXXXXXXXXXXX.........XX.............. 17
XLXI_1/cnt<11> XXXXXXXXXXXXXXX.........XX.............. 17
XLXI_1/cnt<10> XXXXXXXXXXXXXXX.........XX.............. 17
XLXI_1/cnt<6> XXXXXXXXXXXXXXX.........XX.............. 17
dataout<6> ...............XXXX..................... 4
XLXI_1/cnt<5> X.....XXXX..............XX.............. 7
XLXN_26<0> .......................X.X.............. 2
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FTCPE_XLXI_1/cnt0: FTCPE port map (XLXI_1/cnt(0),'1',clk,NOT rst,'0');
FTCPE_XLXI_1/cnt1: FTCPE port map (XLXI_1/cnt(1),XLXI_1/cnt(0),clk,NOT rst,'0');
FTCPE_XLXI_1/cnt2: FTCPE port map (XLXI_1/cnt(2),XLXI_1/cnt_T(2),clk,NOT rst,'0');
XLXI_1/cnt_T(2) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(1));
FTCPE_XLXI_1/cnt3: FTCPE port map (XLXI_1/cnt(3),XLXI_1/cnt(4).EXP,clk,NOT rst,'0');
FTCPE_XLXI_1/cnt4: FTCPE port map (XLXI_1/cnt(4),XLXI_1/cnt_T(4),clk,NOT rst,'0');
XLXI_1/cnt_T(4) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3));
FTCPE_XLXI_1/cnt5: FTCPE port map (XLXI_1/cnt(5),XLXI_1/cnt_T(5),clk,NOT rst,'0');
XLXI_1/cnt_T(5) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4));
FTCPE_XLXI_1/cnt6: FTCPE port map (XLXI_1/cnt(6),XLXI_1/cnt_T(6),clk,NOT rst,'0');
XLXI_1/cnt_T(6) <= ((NOT XLXI_1/cnt(0))
OR (NOT XLXI_1/cnt(1))
OR (NOT XLXI_1/cnt(2))
OR (XLXI_1/cnt(10).EXP)
OR (dataout_6_OBUF.EXP));
FTCPE_XLXI_1/cnt7: FTCPE port map (XLXI_1/cnt(7),XLXI_1/cnt_T(7),clk,NOT rst,'0');
XLXI_1/cnt_T(7) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6))
OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(7) AND
XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
FTCPE_XLXI_1/cnt8: FTCPE port map (XLXI_1/cnt(8),XLXI_1/cnt_T(8),clk,NOT rst,'0');
XLXI_1/cnt_T(8) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND
XLXI_1/cnt(7))
OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(7) AND
XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
FTCPE_XLXI_1/cnt9: FTCPE port map (XLXI_1/cnt(9),XLXI_1/cnt_T(9),clk,NOT rst,'0');
XLXI_1/cnt_T(9) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND
XLXI_1/cnt(7) AND XLXI_1/cnt(8));
FTCPE_XLXI_1/cnt10: FTCPE port map (XLXI_1/cnt(10),XLXI_1/cnt_T(10),clk,NOT rst,'0');
XLXI_1/cnt_T(10) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND
XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND XLXI_1/cnt(9))
OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND NOT XLXI_1/cnt(6) AND
XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
FTCPE_XLXI_1/cnt11: FTCPE port map (XLXI_1/cnt(11),XLXI_1/cnt_T(11),clk,NOT rst,'0');
XLXI_1/cnt_T(11) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(1) AND
XLXI_1/cnt(2) AND XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND
XLXI_1/cnt(6) AND XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND XLXI_1/cnt(9))
OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND NOT XLXI_1/cnt(6) AND
XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
FTCPE_XLXI_1/cnt12: FTCPE port map (XLXI_1/cnt(12),XLXI_1/cnt_T(12),clk,NOT rst,'0');
XLXI_1/cnt_T(12) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND
XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND
XLXI_1/cnt(9))
OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND NOT XLXI_1/cnt(6) AND
XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
FTCPE_XLXI_1/cnt13: FTCPE port map (XLXI_1/cnt(13),XLXI_1/cnt_T(13),clk,NOT rst,'0');
XLXI_1/cnt_T(13) <= (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(12) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND XLXI_1/cnt(3) AND
XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND XLXI_1/cnt(7) AND
XLXI_1/cnt(8) AND XLXI_1/cnt(9));
FTCPE_XLXI_1/cnt14: FTCPE port map (XLXI_1/cnt(14),XLXI_1/cnt_T(14),clk,NOT rst,'0');
XLXI_1/cnt_T(14) <= ((XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(12) AND XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND XLXI_1/cnt(6) AND
XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND XLXI_1/cnt(9))
OR (XLXI_1/cnt(0) AND XLXI_1/cnt(10) AND XLXI_1/cnt(11) AND
XLXI_1/cnt(12) AND NOT XLXI_1/cnt(13) AND XLXI_1/cnt(1) AND XLXI_1/cnt(2) AND
XLXI_1/cnt(3) AND XLXI_1/cnt(4) AND XLXI_1/cnt(5) AND NOT XLXI_1/cnt(6) AND
XLXI_1/cnt(7) AND XLXI_1/cnt(8) AND NOT XLXI_1/cnt(9) AND XLXI_1/cnt(14)));
FTCPE_XLXI_3/cnt0: FTCPE port map (XLXI_3/cnt(0),'1',clk,NOT rst,'0');
FTCPE_XLXI_3/cnt1: FTCPE port map (XLXI_3/cnt(1),XLXI_3/cnt(0),clk,NOT rst,'0');
FTCPE_XLXI_3/cnt2: FTCPE port map (XLXI_3/cnt(2),XLXI_3/cnt_T(2),clk,NOT rst,'0');
XLXI_3/cnt_T(2) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1));
FTCPE_XLXI_3/cnt3: FTCPE port map (XLXI_3/cnt(3),XLXI_3/cnt_T(3),clk,NOT rst,'0');
XLXI_3/cnt_T(3) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2));
FTCPE_XLXI_3/cnt4: FTCPE port map (XLXI_3/cnt(4),XLXI_3/cnt_T(4),clk,NOT rst,'0');
XLXI_3/cnt_T(4) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND
XLXI_3/cnt(3));
FTCPE_XLXI_3/cnt5: FTCPE port map (XLXI_3/cnt(5),XLXI_3/cnt_T(5),clk,NOT rst,'0');
XLXI_3/cnt_T(5) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND
XLXI_3/cnt(3) AND XLXI_3/cnt(4));
FTCPE_XLXI_3/cnt6: FTCPE port map (XLXI_3/cnt(6),XLXI_3/cnt_T(6),clk,NOT rst,'0');
XLXI_3/cnt_T(6) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND
XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5));
FTCPE_XLXI_3/cnt7: FTCPE port map (XLXI_3/cnt(7),XLXI_3/cnt_T(7),clk,NOT rst,'0');
XLXI_3/cnt_T(7) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND
XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6));
FTCPE_XLXI_3/cnt8: FTCPE port map (XLXI_3/cnt(8),XLXI_3/cnt_T(8),clk,NOT rst,'0');
XLXI_3/cnt_T(8) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND
XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND
XLXI_3/cnt(7));
FTCPE_XLXI_3/cnt9: FTCPE port map (XLXI_3/cnt(9),XLXI_3/cnt_T(9),clk,NOT rst,'0');
XLXI_3/cnt_T(9) <= ((NOT XLXI_3/cnt(0))
OR (NOT XLXI_3/cnt(1))
OR (NOT XLXI_3/cnt(2))
OR (XLXI_3/cnt(3).EXP)
OR (EXP12_.EXP));
FTCPE_XLXI_3/cnt10: FTCPE port map (XLXI_3/cnt(10),XLXI_3/cnt_T(10),clk,NOT rst,'0');
XLXI_3/cnt_T(10) <= (XLXI_3/cnt(0) AND XLXI_3/cnt(1) AND XLXI_3/cnt(2) AND
XLXI_3/cnt(3) AND XLXI_3/cnt(4) AND XLXI_3/cnt(5) AND XLXI_3/cnt(6) AND
XLXI_3/cnt(7) AND XLXI_3/cnt(8) AND XLXI_3/cnt(9));
FTCPE_XLXI_3/cnt11: FTCPE port map (XLXI_3/cnt(11),XLXI_3/cnt_T(11),clk,NOT rst,'0');
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