📄 clock.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: clock Date: 2-21-2006, 12:41PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
92 /144 ( 64%) 370 /720 ( 51%) 156/432 ( 36%) 84 /144 ( 58%) 18 /117 ( 15%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 15/18 28/54 77/90 0/15
FB2 13/18 28/54 59/90 0/15
FB3 11/18 18/54 34/90 0/15
FB4 18/18* 28/54 68/90 6/15
FB5 0/18 0/54 0/90 0/14
FB6 18/18* 28/54 55/90 9/13
FB7 0/18 0/54 0/90 0/15
FB8 17/18 26/54 77/90 1/15
----- ----- ----- -----
92/144 156/432 370/720 16/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 18 109
Output : 16 16 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 18 18
** Power Data **
There are 92 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 16 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
dataout<1> 3 4 FB4_1 118 I/O O STD FAST
en<5> 3 5 FB4_2 126 I/O O STD FAST RESET
en<1> 3 5 FB4_3 133 I/O O STD FAST RESET
en<6> 3 5 FB4_9 131 I/O O STD FAST RESET
en<7> 3 5 FB4_11 132 I/O O STD FAST RESET
en<0> 3 5 FB4_12 134 I/O O STD FAST RESET
dataout<7> 4 4 FB6_2 106 I/O O STD FAST
dataout<5> 3 4 FB6_4 111 I/O O STD FAST
dataout<4> 4 4 FB6_8 113 I/O O STD FAST
dataout<2> 4 4 FB6_9 116 I/O O STD FAST
dataout<3> 4 4 FB6_10 115 I/O O STD FAST
dataout<0> 0 0 FB6_11 119 I/O O STD FAST
en<4> 3 5 FB6_12 120 I/O O STD FAST RESET
en<3> 3 5 FB6_15 124 I/O O STD FAST RESET
en<2> 3 5 FB6_17 125 I/O O STD FAST RESET
dataout<6> 4 4 FB8_16 107 I/O O STD FAST
** 76 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXI_3/cnt<9> 12 28 FB1_1 STD RESET
XLXI_3/cnt<3> 3 5 FB1_2 STD RESET
XLXI_3/cnt<24> 3 26 FB1_3 STD RESET
XLXI_3/cnt<23> 3 25 FB1_4 STD RESET
XLXI_3/cnt<20> 3 22 FB1_5 STD RESET
XLXI_3/cnt<19> 3 21 FB1_6 STD RESET
XLXI_3/cnt<25> 4 28 FB1_7 STD RESET
XLXI_3/cnt<22> 4 28 FB1_8 STD RESET
XLXI_3/cnt<21> 4 28 FB1_9 STD RESET
XLXI_3/cnt<17> 4 28 FB1_10 STD RESET
XLXI_3/cnt<14> 4 28 FB1_11 STD RESET
XLXI_3/cnt<12> 4 28 FB1_12 STD RESET
XLXI_3/cnt<11> 4 28 FB1_13 STD RESET
XLXN_9 19 28 FB1_15 STD RESET
XLXI_3/cnt<4> 3 6 FB1_17 STD RESET
XLXN_13<1> 8 11 FB2_1 STD RESET
XLXN_13<2> 8 11 FB2_4 STD RESET
XLXN_20<1> 6 10 FB2_5 STD RESET
XLXN_19<2> 5 10 FB2_6 STD RESET
XLXN_20<3> 4 10 FB2_7 STD RESET
XLXN_29<3> 4 9 FB2_8 STD RESET
XLXI_6/cnt<1> 3 3 FB2_9 STD RESET
XLXI_6/cnt<2> 3 4 FB2_10 STD RESET
XLXN_26<2> 3 4 FB2_11 STD RESET
XLXN_29<0> 3 6 FB2_12 STD RESET
XLXI_6/cnt<0> 2 2 FB2_13 STD RESET
XLXN_19<0> 2 2 FB2_14 STD RESET
XLXN_13<0> 8 11 FB2_18 STD RESET
XLXN_24<0> 2 2 FB3_8 STD RESET
XLXI_3/cnt<0> 2 2 FB3_9 STD RESET
XLXI_1/cnt<0> 2 2 FB3_10 STD RESET
XLXN_7 3 10 FB3_11 STD RESET
XLXN_24<2> 3 4 FB3_12 STD RESET
XLXI_3/cnt<2> 3 4 FB3_13 STD RESET
XLXI_3/cnt<1> 3 3 FB3_14 STD RESET
XLXI_1/cnt<2> 3 4 FB3_15 STD RESET
XLXI_1/cnt<1> 3 3 FB3_16 STD RESET
XLXN_29<2> 5 10 FB3_17 STD RESET
XLXN_29<1> 5 10 FB3_18 STD RESET
XLXN_6 3 10 FB4_4 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXN_22<0> 3 6 FB4_5 STD RESET
XLXN_20<2> 3 8 FB4_6 STD RESET
XLXN_20<0> 3 6 FB4_7 STD RESET
XLXN_24<3> 4 6 FB4_8 STD RESET
XLXN_24<1> 4 6 FB4_10 STD RESET
XLXN_22<3> 4 9 FB4_13 STD RESET
XLXN_19<3> 4 6 FB4_14 STD RESET
XLXN_19<1> 4 6 FB4_15 STD RESET
XLXN_22<2> 5 10 FB4_16 STD RESET
XLXN_22<1> 5 10 FB4_17 STD RESET
XLXN_13<3> 8 11 FB4_18 STD RESET
XLXI_3/cnt<8> 3 10 FB6_1 STD RESET
XLXI_3/cnt<7> 3 9 FB6_3 STD RESET
XLXI_3/cnt<6> 3 8 FB6_5 STD RESET
XLXI_3/cnt<5> 3 7 FB6_6 STD RESET
XLXI_3/cnt<18> 3 20 FB6_7 STD RESET
XLXI_3/cnt<16> 3 18 FB6_13 STD RESET
XLXI_3/cnt<15> 3 17 FB6_14 STD RESET
XLXI_3/cnt<13> 3 15 FB6_16 STD RESET
XLXI_3/cnt<10> 3 12 FB6_18 STD RESET
XLXI_1/cnt<9> 3 11 FB8_1 STD RESET
XLXI_1/cnt<4> 3 6 FB8_2 STD RESET
XLXI_1/cnt<3> 3 5 FB8_3 STD RESET
XLXN_10 15 17 FB8_4 STD RESET
XLXI_1/cnt<13> 3 15 FB8_6 STD RESET
XLXN_26<3> 4 6 FB8_7 STD RESET
XLXN_26<1> 4 6 FB8_8 STD RESET
XLXI_1/cnt<8> 4 17 FB8_9 STD RESET
XLXI_1/cnt<7> 4 17 FB8_10 STD RESET
XLXI_1/cnt<14> 4 17 FB8_11 STD RESET
XLXI_1/cnt<12> 4 17 FB8_12 STD RESET
XLXI_1/cnt<11> 4 17 FB8_13 STD RESET
XLXI_1/cnt<10> 4 17 FB8_14 STD RESET
XLXI_1/cnt<6> 9 17 FB8_15 STD RESET
XLXI_1/cnt<5> 3 7 FB8_17 STD RESET
XLXN_26<0> 2 2 FB8_18 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
rst FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 28/26
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
XLXI_3/cnt<9> 12 7<- 0 0 FB1_1 23 I/O (b)
XLXI_3/cnt<3> 3 0 /\2 0 FB1_2 16 I/O (b)
XLXI_3/cnt<24> 3 0 0 2 FB1_3 17 I/O (b)
XLXI_3/cnt<23> 3 0 0 2 FB1_4 25 I/O (b)
XLXI_3/cnt<20> 3 0 0 2 FB1_5 19 I/O (b)
XLXI_3/cnt<19> 3 0 0 2 FB1_6 20 I/O (b)
XLXI_3/cnt<25> 4 0 0 1 FB1_7 (b) (b)
XLXI_3/cnt<22> 4 0 0 1 FB1_8 21 I/O (b)
XLXI_3/cnt<21> 4 0 0 1 FB1_9 22 I/O (b)
XLXI_3/cnt<17> 4 0 0 1 FB1_10 31 I/O (b)
XLXI_3/cnt<14> 4 0 0 1 FB1_11 24 I/O (b)
XLXI_3/cnt<12> 4 0 \/1 0 FB1_12 26 I/O (b)
XLXI_3/cnt<11> 4 1<- \/2 0 FB1_13 (b) (b)
(unused) 0 0 \/5 0 FB1_14 27 I/O (b)
XLXN_9 19 14<- 0 0 FB1_15 28 I/O (b)
(unused) 0 0 /\5 0 FB1_16 35 I/O (b)
XLXI_3/cnt<4> 3 0 /\2 0 FB1_17 30 GCK/I/O (b)
(unused) 0 0 \/5 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: XLXI_3/cnt<0> 11: XLXI_3/cnt<19> 20: XLXI_3/cnt<3>
2: XLXI_3/cnt<10> 12: XLXI_3/cnt<1> 21: XLXI_3/cnt<4>
3: XLXI_3/cnt<11> 13: XLXI_3/cnt<20> 22: XLXI_3/cnt<5>
4: XLXI_3/cnt<12> 14: XLXI_3/cnt<21> 23: XLXI_3/cnt<6>
5: XLXI_3/cnt<13> 15: XLXI_3/cnt<22> 24: XLXI_3/cnt<7>
6: XLXI_3/cnt<14> 16: XLXI_3/cnt<23> 25: XLXI_3/cnt<8>
7: XLXI_3/cnt<15> 17: XLXI_3/cnt<24> 26: XLXI_3/cnt<9>
8: XLXI_3/cnt<16> 18: XLXI_3/cnt<25> 27: clk
9: XLXI_3/cnt<17> 19: XLXI_3/cnt<2> 28: rst
10: XLXI_3/cnt<18>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
XLXI_3/cnt<9> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXI_3/cnt<3> X..........X......X.......XX............ 5
XLXI_3/cnt<24> XXXXXXXXXXXXXXXX..XXXXXXXXXX............ 26
XLXI_3/cnt<23> XXXXXXXXXXXXXXX...XXXXXXXXXX............ 25
XLXI_3/cnt<20> XXXXXXXXXXXX......XXXXXXXXXX............ 22
XLXI_3/cnt<19> XXXXXXXXXX.X......XXXXXXXXXX............ 21
XLXI_3/cnt<25> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXI_3/cnt<22> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXI_3/cnt<21> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXI_3/cnt<17> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXI_3/cnt<14> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXI_3/cnt<12> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXI_3/cnt<11> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXN_9 XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
XLXI_3/cnt<4> X..........X......XX......XX............ 6
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