clock.par

vhdl经典源代码——时钟设计

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

WXY::  Fri Mar 17 10:23:48 2006

par -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd clock.pcf 


Constraints file: clock.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "clock" is an NCD, version 3.1, device xc3s400, package pq208, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "ADVANCED 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            16 out of 141    11%
      Number of LOCed IOBs            16 out of 16    100%

   Number of Slices                   97 out of 3584    2%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98989b) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.8
...
Phase 4.8 (Checksum:994f6b) REAL time: 4 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 4 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 4 secs 

Writing design to file clock.ncd


Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 649 unrouted;       REAL time: 4 secs 

Phase 2: 623 unrouted;       REAL time: 4 secs 

Phase 3: 185 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 


WARNING:CLK Net:XLXI_3/qout
may have excessive skew because 5 CLK pins
failed to route using a CLK template.

WARNING:CLK Net:XLXI_16/carry
may have excessive skew because 5 CLK pins
failed to route using a CLK template.

WARNING:CLK Net:XLXI_17/carry
may have excessive skew because 6 CLK pins
failed to route using a CLK template.

WARNING:CLK Net:XLXI_1/qout
may have excessive skew because 9 CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 2 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX1| No   |   25 |  0.018     |  0.901      |
+---------------------+--------------+------+------+------------+-------------+
|         XLXI_3/qout |         Local|      |    5 |  0.622     |  2.312      |
+---------------------+--------------+------+------+------------+-------------+
|       XLXI_17/carry |         Local|      |    6 |  0.009     |  1.515      |
+---------------------+--------------+------+------+------------+-------------+
|         XLXI_1/qout |         Local|      |    9 |  0.916     |  2.138      |
+---------------------+--------------+------+------+------------+-------------+
|       XLXI_16/carry |         Local|      |    5 |  0.009     |  1.213      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  75 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file clock.ncd



PAR done!