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vhdl经典源代码——时钟设计

Compiling vhdl file "E:/temp/95144/vhdl/clock/fen100.vhd" in Library work.
Entity <fen100> compiled.
Entity <fen100> (Architecture <behave>) compiled.
Compiling vhdl file "E:/temp/95144/vhdl/clock/fen24.vhd" in Library work.
Entity <fen24> compiled.
Entity <fen24> (Architecture <behave>) compiled.
Compiling vhdl file "E:/temp/95144/vhdl/clock/fen1.vhd" in Library work.
Entity <fen1> compiled.
Entity <fen1> (Architecture <behave>) compiled.
Compiling vhdl file "E:/temp/95144/vhdl/clock/decode47.vhd" in Library work.
Entity <decode47> compiled.
Entity <decode47> (Architecture <behave>) compiled.
Compiling vhdl file "E:/temp/95144/vhdl/clock/sel.vhd" in Library work.
Entity <sel> compiled.
Entity <sel> (Architecture <behave>) compiled.
Compiling vhdl file "E:/temp/95144/vhdl/clock/fen60.vhd" in Library work.
Entity <fen60> compiled.
Entity <fen60> (Architecture <behave>) compiled.
Compiling vhdl file "E:/temp/95144/vhdl/clock/clock.vhf" in Library work.
Entity <clock> compiled.
Entity <clock> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <BEHAVIORAL>).
WARNING:Xst:753 - "E:/temp/95144/vhdl/clock/clock.vhf" line 102: Unconnected output port 'carry' of component 'fen24'.
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <fen100> (Architecture <behave>).
Entity <fen100> analyzed. Unit <fen100> generated.

Analyzing Entity <fen24> (Architecture <behave>).
WARNING:Xst:819 - "E:/temp/95144/vhdl/clock/fen24.vhd" line 31: The following signals are missing in the process sensitivity list:
   tem1, tem2.
Entity <fen24> analyzed. Unit <fen24> generated.

Analyzing Entity <fen1> (Architecture <behave>).
Entity <fen1> analyzed. Unit <fen1> generated.

Analyzing Entity <decode47> (Architecture <behave>).
Entity <decode47> analyzed. Unit <decode47> generated.

Analyzing Entity <sel> (Architecture <behave>).
Entity <sel> analyzed. Unit <sel> generated.

Analyzing Entity <fen60> (Architecture <behave>).
WARNING:Xst:819 - "E:/temp/95144/vhdl/clock/fen60.vhd" line 30: The following signals are missing in the process sensitivity list:
   tem1, tem2.
Entity <fen60> analyzed. Unit <fen60> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fen60>.
    Related source file is "E:/temp/95144/vhdl/clock/fen60.vhd".
    Found 1-bit register for signal <carry>.
    Found 4-bit up counter for signal <tem1>.
    Found 4-bit up counter for signal <tem2>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <fen60> synthesized.


Synthesizing Unit <sel>.
    Related source file is "E:/temp/95144/vhdl/clock/sel.vhd".
    Found 4-bit register for signal <qout>.
    Found 8-bit register for signal <sel>.
    Found 8-bit shifter rotate left for signal <$n0003> created at line 50.
    Found 4-bit 8-to-1 multiplexer for signal <$n0004> created at line 50.
    Found 3-bit adder for signal <$n0005> created at line 48.
    Found 3-bit register for signal <cnt>.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   1 Combinational logic shifter(s).
Unit <sel> synthesized.


Synthesizing Unit <decode47>.
    Related source file is "E:/temp/95144/vhdl/clock/decode47.vhd".
    Found 16x8-bit ROM for signal <qout>.
    Summary:
	inferred   1 ROM(s).
Unit <decode47> synthesized.


Synthesizing Unit <fen1>.
    Related source file is "E:/temp/95144/vhdl/clock/fen1.vhd".
    Found 1-bit register for signal <qout>.
    Found 26-bit adder for signal <$n0003> created at line 35.
    Found 26-bit comparator lessequal for signal <$n0005>.
    Found 26-bit register for signal <cnt>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <fen1> synthesized.


Synthesizing Unit <fen24>.
    Related source file is "E:/temp/95144/vhdl/clock/fen24.vhd".
    Found 1-bit register for signal <carry>.
    Found 4-bit adder for signal <$n0008> created at line 51.
    Found 4-bit adder for signal <$n0009> created at line 48.
    Found 4-bit register for signal <tem1>.
    Found 4-bit register for signal <tem2>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <fen24> synthesized.


Synthesizing Unit <fen100>.
    Related source file is "E:/temp/95144/vhdl/clock/fen100.vhd".
    Found 1-bit register for signal <qout>.
    Found 15-bit adder for signal <$n0003> created at line 36.
    Found 15-bit comparator lessequal for signal <$n0005>.
    Found 15-bit register for signal <cnt>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <fen100> synthesized.


Synthesizing Unit <clock>.
    Related source file is "E:/temp/95144/vhdl/clock/clock.vhf".
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 5
 15-bit adder                      : 1
 26-bit adder                      : 1
 3-bit adder                       : 1
 4-bit adder                       : 2
# Counters                         : 4
 4-bit up counter                  : 4
# Registers                        : 12
 1-bit register                    : 5
 15-bit register                   : 1
 26-bit register                   : 1
 3-bit register                    : 1
 4-bit register                    : 3
 8-bit register                    : 1
# Comparators                      : 2
 15-bit comparator lessequal       : 1
 26-bit comparator lessequal       : 1
# Multiplexers                     : 1
 4-bit 8-to-1 multiplexer          : 1
# Logic shifters                   : 1
 8-bit shifter rotate left         : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <carry> is unconnected in block <XLXI_2>.

Optimizing unit <clock> ...

Optimizing unit <fen24> ...

Optimizing unit <fen100> ...
  implementation constraint: INIT=r	 : cnt_14
  implementation constraint: INIT=r	 : cnt_13
  implementation constraint: INIT=r	 : cnt_0
  implementation constraint: INIT=r	 : cnt_1
  implementation constraint: INIT=r	 : cnt_2
  implementation constraint: INIT=r	 : cnt_3
  implementation constraint: INIT=r	 : cnt_4
  implementation constraint: INIT=r	 : cnt_5
  implementation constraint: INIT=r	 : cnt_6
  implementation constraint: INIT=r	 : cnt_7
  implementation constraint: INIT=r	 : cnt_8
  implementation constraint: INIT=r	 : cnt_9
  implementation constraint: INIT=r	 : cnt_10
  implementation constraint: INIT=r	 : cnt_11
  implementation constraint: INIT=r	 : cnt_12

Optimizing unit <decode47> ...

Optimizing unit <fen60> ...

Optimizing unit <sel> ...
  implementation constraint: INIT=r	 : cnt_1
  implementation constraint: INIT=r	 : cnt_0
  implementation constraint: INIT=r	 : cnt_2

Optimizing unit <fen1> ...
  implementation constraint: INIT=r	 : cnt_25
  implementation constraint: INIT=r	 : cnt_24
  implementation constraint: INIT=r	 : cnt_0
  implementation constraint: INIT=r	 : cnt_1
  implementation constraint: INIT=r	 : cnt_2
  implementation constraint: INIT=r	 : cnt_3
  implementation constraint: INIT=r	 : cnt_4
  implementation constraint: INIT=r	 : cnt_5
  implementation constraint: INIT=r	 : cnt_6
  implementation constraint: INIT=r	 : cnt_7
  implementation constraint: INIT=r	 : cnt_8
  implementation constraint: INIT=r	 : cnt_9
  implementation constraint: INIT=r	 : cnt_10
  implementation constraint: INIT=r	 : cnt_11
  implementation constraint: INIT=r	 : cnt_12
  implementation constraint: INIT=r	 : cnt_13
  implementation constraint: INIT=r	 : cnt_14
  implementation constraint: INIT=r	 : cnt_15
  implementation constraint: INIT=r	 : cnt_16
  implementation constraint: INIT=r	 : cnt_17
  implementation constraint: INIT=r	 : cnt_18
  implementation constraint: INIT=r	 : cnt_19
  implementation constraint: INIT=r	 : cnt_20
  implementation constraint: INIT=r	 : cnt_21
  implementation constraint: INIT=r	 : cnt_22
  implementation constraint: INIT=r	 : cnt_23
WARNING:Xst:1291 - FF/Latch <carry> is unconnected in block <XLXI_2>.




Started process "Translate".

Release 7.1.04i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -i -p xc9500xl clock.ngc clock.ngd 

Reading NGO file 'E:/temp/95144/vhdl/clock/clock.ngc' ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "clock.ngd" ...

Writing NGDBUILD log file "clock.bld"...

NGDBUILD done.




Started process "Fit".

Release 7.1.04i - CPLD Optimizer/Partitioner H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Considering device XC95144XL-10-TQ144.
Flattening design..
Timing optimization......
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 92 equations into 8 function blocks....................................................................

Design clock has been optimized and fit into device XC95144XL-10-TQ144.




Started process "Generate Programming File".

Release 7.1.04i - Programming File Generator H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Started process "Generate Timing".

Release 7.1.04i - Timing Report Generator H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for
analysis.
Path tracing ..........
The number of paths traced: 1128.

......
The number of paths traced: 2257.

Checking for asynchronous logic...
No asynchronous logic found.
Generating TA GUI report ...
Generating detailed paths report ...

e:\temp\95144\vhdl\clock/clock_html/tim/timing_report.htm has been created.




Started process "Generate HTML report".

Release 7.1.04i - CPLD HTML Report Processor H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.






Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/95144/vhdl/clock/fen100.vhd" in Library work.
Architecture behave of Entity fen100 is up to date.
Compiling vhdl file "E:/temp/95144/vhdl/clock/fen24.vhd" in Library work.
Architecture behave of Entity fen24 is up to date.
Compiling vhdl file "E:/temp/95144/vhdl/clock/fen1.vhd" in Library work.
Architecture behave of Entity fen1 is up to date.
Compiling vhdl file "E:/temp/95144/vhdl/clock/decode47.vhd" in Library work.
Architecture behave of Entity decode47 is up to date.
Compiling vhdl file "E:/temp/95144/vhdl/clock/sel.vhd" in Library work.
Architecture behave of Entity sel is up to date.
Compiling vhdl file "E:/temp/95144/vhdl/clock/fen60.vhd" in Library work.
Architecture behave of Entity fen60 is up to date.
Compiling vhdl file "E:/temp/95144/vhdl/clock/clock.vhf" in Library work.
Entity <clock> compiled.
Entity <clock> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <behavioral>).
WARNING:Xst:753 - "E:/temp/95144/vhdl/clock/clock.vhf" line 102: Unconnected output port 'carry' of component 'fen24'.
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <fen100> (Architecture <behave>).
Entity <fen100> analyzed. Unit <fen100> generated.

Analyzing Entity <fen24> (Architecture <behave>).
WARNING:Xst:819 - "E:/temp/95144/vhdl/clock/fen24.vhd" line 31: The following signals are missing in the process sensitivity list:
   tem1, tem2.
Entity <fen24> analyzed. Unit <fen24> generated.

Analyzing Entity <fen1> (Architecture <behave>).
Entity <fen1> analyzed. Unit <fen1> generated.

Analyzing Entity <decode47> (Architecture <behave>).