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vhdl经典源代码——时钟设计

	inferred   1 Counter(s).
	inferred   8 D-type flip-flop(s).
	inferred   7 Adder/Subtractor(s).
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 7
 26-bit adder                      : 1
 4-bit adder                       : 6
# Counters                         : 1
 16-bit up counter                 : 1
# Registers                        : 15
 1-bit register                    : 8
 26-bit register                   : 1
 4-bit register                    : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clock> ...




Started process "Translate".

Release 7.1.04i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd 

Reading NGO file 'E:/temp/95144/vhdl/clock/clock.ngc' ...

Applying constraints in "clock.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "clock.ngd" ...

Writing NGDBUILD log file "clock.bld"...

NGDBUILD done.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/95144/vhdl/clock/clock.vhd" in Library work.
Architecture arch of Entity clock is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <arch>).
WARNING:Xst:819 - "E:/temp/95144/vhdl/clock/clock.vhd" line 64: The following signals are missing in the process sensitivity list:
   en_xhdl2.
INFO:Xst:1304 - Contents of register <dataout_buf2> in unit <clock> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <dataout_buf5> in unit <clock> never changes during circuit operation. The register is replaced by logic.
Entity <clock> analyzed. Unit <clock> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clock>.
    Related source file is "E:/temp/95144/vhdl/clock/clock.vhd".
WARNING:Xst:1780 - Signal <cntled> is never used or assigned.
    Found 16x8-bit ROM for signal <dataout>.
    Found 4-bit adder for signal <$n0021> created at line 118.
    Found 4-bit adder for signal <$n0022> created at line 122.
    Found 4-bit adder for signal <$n0023> created at line 126.
    Found 4-bit adder for signal <$n0024> created at line 130.
    Found 4-bit adder for signal <$n0025> created at line 134.
    Found 4-bit adder for signal <$n0026> created at line 138.
    Found 26-bit adder for signal <$n0027> created at line 97.
    Found 26-bit register for signal <cnt>.
    Found 16-bit up counter for signal <cnt_scan>.
    Found 4-bit register for signal <dataout_buf0>.
    Found 4-bit register for signal <dataout_buf1>.
    Found 4-bit register for signal <dataout_buf3>.
    Found 4-bit register for signal <dataout_buf4>.
    Found 4-bit register for signal <dataout_buf6>.
    Found 4-bit register for signal <dataout_buf7>.
    Found 8-bit register for signal <en_xhdl2>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred   8 D-type flip-flop(s).
	inferred   7 Adder/Subtractor(s).
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 7
 26-bit adder                      : 1
 4-bit adder                       : 6
# Counters                         : 1
 16-bit up counter                 : 1
# Registers                        : 15
 1-bit register                    : 8
 26-bit register                   : 1
 4-bit register                    : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clock> ...




Started process "Translate".

Release 7.1.04i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd 

Reading NGO file 'E:/temp/95144/vhdl/clock/clock.ngc' ...

Applying constraints in "clock.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "clock.ngd" ...

Writing NGDBUILD log file "clock.bld"...

NGDBUILD done.




Started process "Fit".

Release 7.1.04i - CPLD Optimizer/Partitioner H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Considering device XC95144XL-10-TQ144.
Flattening design..
Multi-level logic optimization...
Timing optimization.........................................................................................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 87 equations into 8 function blocks........................................................................................................................................................................................................................WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<7> to allow all signals assigned to this function block to be
   placed.
..........................................................................................................ERROR:Cpld:892 - Cannot place signal $OpTx$DEC_dataout_code<3>/dataout_cod$26.
   Consider reducing the collapsing input limit or the product term limit to
   prevent the fitter from creating high input and/or high product term
   functions.

ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
   the selected implementation options.
ERROR: Fit failed
Reason: 

Started process "Generate HTML report".

Release 7.1.04i - CPLD HTML Report Processor H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Process "Fit" did not complete.


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Started process "Create Schematic Symbol".

Compiling vhdl file "E:/temp/95144/vhdl/clock/decode47.vhd" in Library work.
Entity <decode47> compiled.
Entity <decode47> (Architecture <behave>) compiled.
tdtfi(vhdl) completed successfully.






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Started process "Create Schematic Symbol".

Compiling vhdl file "E:/temp/95144/vhdl/clock/fen1.vhd" in Library work.
Entity <fen1> compiled.
Entity <fen1> (Architecture <behave>) compiled.
tdtfi(vhdl) completed successfully.






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Started process "Create Schematic Symbol".

Compiling vhdl file "E:/temp/95144/vhdl/clock/fen100.vhd" in Library work.
Entity <fen100> compiled.
Entity <fen100> (Architecture <behave>) compiled.
tdtfi(vhdl) completed successfully.






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Started process "Create Schematic Symbol".

Compiling vhdl file "E:/temp/95144/vhdl/clock/fen24.vhd" in Library work.
Entity <fen24> compiled.
Entity <fen24> (Architecture <behave>) compiled.
tdtfi(vhdl) completed successfully.






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Started process "Create Schematic Symbol".

Compiling vhdl file "E:/temp/95144/vhdl/clock/fen60.vhd" in Library work.
Entity <fen60> compiled.
Entity <fen60> (Architecture <behave>) compiled.
tdtfi(vhdl) completed successfully.






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Started process "Create Schematic Symbol".

Compiling vhdl file "E:/temp/95144/vhdl/clock/sel.vhd" in Library work.
Entity <sel> compiled.
ERROR:HDLParsers:3370 - "E:/temp/95144/vhdl/clock/sel.vhd" Line 63. Value 6 is
   not included in the range, 0 to 5, of cnt.
ERROR:HDLParsers:3370 - "E:/temp/95144/vhdl/clock/sel.vhd" Line 65. Value 7 is
   not included in the range, 0 to 5, of cnt.
tdtfi(vhdl) completed successfully.






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Started process "Create Schematic Symbol".

Compiling vhdl file "E:/temp/95144/vhdl/clock/sel.vhd" in Library work.
Entity <sel> compiled.
Entity <sel> (Architecture <behave>) compiled.
tdtfi(vhdl) completed successfully.






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Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/CLOCK is now defined in a different file: was E:/temp/95144/vhdl/clock/clock.vhd, now is E:/temp/95144/vhdl/clock/clock.vhf