__projnav.log

vhdl经典源代码——时钟设计

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/95144/vhdl/clock/clock.vhd" in Library work.
Entity <clock> compiled.
Entity <clock> (Architecture <arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <arch>).
WARNING:Xst:819 - "E:/temp/95144/vhdl/clock/clock.vhd" line 84: The following signals are missing in the process sensitivity list:
   en_xhdl2.
INFO:Xst:1304 - Contents of register <dataout_buf2> in unit <clock> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <dataout_buf5> in unit <clock> never changes during circuit operation. The register is replaced by logic.
Entity <clock> analyzed. Unit <clock> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clock>.
    Related source file is "E:/temp/95144/vhdl/clock/clock.vhd".
    Found 16x8-bit ROM for signal <dataout>.
    Found 4-bit adder for signal <$n0022> created at line 138.
    Found 4-bit adder for signal <$n0023> created at line 142.
    Found 4-bit adder for signal <$n0024> created at line 146.
    Found 4-bit adder for signal <$n0025> created at line 150.
    Found 4-bit adder for signal <$n0026> created at line 154.
    Found 4-bit adder for signal <$n0027> created at line 158.
    Found 26-bit adder for signal <$n0028> created at line 117.
    Found 26-bit register for signal <cnt>.
    Found 16-bit up counter for signal <cnt_scan>.
    Found 23-bit up counter for signal <cntled>.
    Found 4-bit register for signal <dataout_buf0>.
    Found 4-bit register for signal <dataout_buf1>.
    Found 4-bit register for signal <dataout_buf3>.
    Found 4-bit register for signal <dataout_buf4>.
    Found 4-bit register for signal <dataout_buf6>.
    Found 4-bit register for signal <dataout_buf7>.
    Found 12-bit register for signal <dataout_tmp>.
    Found 8-bit register for signal <en_xhdl2>.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred  20 D-type flip-flop(s).
	inferred   7 Adder/Subtractor(s).
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 7
 26-bit adder                      : 1
 4-bit adder                       : 6
# Counters                         : 2
 16-bit up counter                 : 1
 23-bit up counter                 : 1
# Registers                        : 27
 1-bit register                    : 20
 26-bit register                   : 1
 4-bit register                    : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clock> ...




Started process "Translate".

Extracting independent architecture files...
Release 7.1.04i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd 

Reading NGO file 'E:/temp/95144/vhdl/clock/clock.ngc' ...

Applying constraints in "clock.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "clock.ngd" ...

Writing NGDBUILD log file "clock.bld"...

NGDBUILD done.




Started process "Fit".

Release 7.1.04i - CPLD Optimizer/Partitioner H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Considering device XC95144XL-10-TQ144.
Flattening design..
Multi-level logic optimization...
Timing optimization....................................................................................................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 122 equations into 8 function blocks.........................................................................................................................................................................................................................................................................................WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<7> to allow all signals assigned to this function block to be
   placed.
...............................................................................................ERROR:Cpld:892 - Cannot place signal cntled<10>. Consider reducing the
   collapsing input limit or the product term limit to prevent the fitter from
   creating high input and/or high product term functions.
..............................
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
   the selected implementation options.
ERROR: Fit failed
Reason: 

Started process "Generate HTML report".

Release 7.1.04i - CPLD HTML Report Processor H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Process "Fit" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/95144/vhdl/clock/clock.vhd" in Library work.
Architecture arch of Entity clock is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <arch>).
WARNING:Xst:819 - "E:/temp/95144/vhdl/clock/clock.vhd" line 84: The following signals are missing in the process sensitivity list:
   en_xhdl2.
INFO:Xst:1304 - Contents of register <dataout_buf2> in unit <clock> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <dataout_buf5> in unit <clock> never changes during circuit operation. The register is replaced by logic.
Entity <clock> analyzed. Unit <clock> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clock>.
    Related source file is "E:/temp/95144/vhdl/clock/clock.vhd".
    Found 16x8-bit ROM for signal <dataout>.
    Found 4-bit adder for signal <$n0022> created at line 138.
    Found 4-bit adder for signal <$n0023> created at line 142.
    Found 4-bit adder for signal <$n0024> created at line 146.
    Found 4-bit adder for signal <$n0025> created at line 150.
    Found 4-bit adder for signal <$n0026> created at line 154.
    Found 4-bit adder for signal <$n0027> created at line 158.
    Found 26-bit adder for signal <$n0028> created at line 117.
    Found 26-bit register for signal <cnt>.
    Found 16-bit up counter for signal <cnt_scan>.
    Found 23-bit up counter for signal <cntled>.
    Found 4-bit register for signal <dataout_buf0>.
    Found 4-bit register for signal <dataout_buf1>.
    Found 4-bit register for signal <dataout_buf3>.
    Found 4-bit register for signal <dataout_buf4>.
    Found 4-bit register for signal <dataout_buf6>.
    Found 4-bit register for signal <dataout_buf7>.
    Found 12-bit register for signal <dataout_tmp>.
    Found 8-bit register for signal <en_xhdl2>.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred  20 D-type flip-flop(s).
	inferred   7 Adder/Subtractor(s).
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 7
 26-bit adder                      : 1
 4-bit adder                       : 6
# Counters                         : 2
 16-bit up counter                 : 1
 23-bit up counter                 : 1
# Registers                        : 27
 1-bit register                    : 20
 26-bit register                   : 1
 4-bit register                    : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clock> ...




Started process "Translate".

Release 7.1.04i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd 

Reading NGO file 'E:/temp/95144/vhdl/clock/clock.ngc' ...

Applying constraints in "clock.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "clock.ngd" ...

Writing NGDBUILD log file "clock.bld"...

NGDBUILD done.




Started process "Fit".

Release 7.1.04i - CPLD Optimizer/Partitioner H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Considering device XC95144XL-10-TQ144.
Flattening design..
Multi-level logic optimization...
Timing optimization....................................................................................................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 122 equations into 8 function blocks.........................................................................................................................................................................................................................................................................................WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<7> to allow all signals assigned to this function block to be
   placed.
...............................................................................................ERROR:Cpld:892 - Cannot place signal cntled<10>. Consider reducing the
   collapsing input limit or the product term limit to prevent the fitter from
   creating high input and/or high product term functions.
..............................
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
   the selected implementation options.
ERROR: Fit failed
Reason: 

Started process "Generate HTML report".

Release 7.1.04i - CPLD HTML Report Processor H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Process "Fit" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/95144/vhdl/clock/clock.vhd" in Library work.
Entity <clock> compiled.
Entity <clock> (Architecture <arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <arch>).
WARNING:Xst:819 - "E:/temp/95144/vhdl/clock/clock.vhd" line 64: The following signals are missing in the process sensitivity list:
   en_xhdl2.
INFO:Xst:1304 - Contents of register <dataout_buf2> in unit <clock> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <dataout_buf5> in unit <clock> never changes during circuit operation. The register is replaced by logic.
Entity <clock> analyzed. Unit <clock> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clock>.
    Related source file is "E:/temp/95144/vhdl/clock/clock.vhd".
WARNING:Xst:1780 - Signal <cntled> is never used or assigned.
    Found 16x8-bit ROM for signal <dataout>.
    Found 4-bit adder for signal <$n0021> created at line 118.
    Found 4-bit adder for signal <$n0022> created at line 122.
    Found 4-bit adder for signal <$n0023> created at line 126.
    Found 4-bit adder for signal <$n0024> created at line 130.
    Found 4-bit adder for signal <$n0025> created at line 134.
    Found 4-bit adder for signal <$n0026> created at line 138.
    Found 26-bit adder for signal <$n0027> created at line 97.
    Found 26-bit register for signal <cnt>.
    Found 16-bit up counter for signal <cnt_scan>.
    Found 4-bit register for signal <dataout_buf0>.
    Found 4-bit register for signal <dataout_buf1>.
    Found 4-bit register for signal <dataout_buf3>.
    Found 4-bit register for signal <dataout_buf4>.
    Found 4-bit register for signal <dataout_buf6>.
    Found 4-bit register for signal <dataout_buf7>.
    Found 8-bit register for signal <en_xhdl2>.
    Summary:
	inferred   1 ROM(s).