clock.cmd_log

vhdl经典源代码——时钟设计

xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper clock.ngd
XSLTProcess "clock_build.xml"
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper clock.ngd
XSLTProcess "clock_build.xml"
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper clock.ngd
XSLTProcess "clock_build.xml"
sch2vhdl -intstyle ise -family xc9500xl -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -i -p xc9500xl clock.ngc clock.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper clock.ngd
hprep6 -s IEEE1149 -n clock -i clock
taengine -f clock -w --format html1 -l e:\temp\95144\vhdl\clock/clock_html/tim/timing_report.htm
XSLTProcess "clock_build.xml"
sch2vhdl -intstyle ise -family xc9500xl -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper clock.ngd
hprep6 -s IEEE1149 -n clock -i clock
taengine -f clock -w --format html1 -l e:\temp\95144\vhdl\clock/clock_html/tim/timing_report.htm
XSLTProcess "clock_build.xml"
sch2vhdl -intstyle ise -family xc9500xl -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper clock.ngd
hprep6 -s IEEE1149 -n clock -i clock
taengine -f clock -w --format html1 -l e:\temp\95144\vhdl\clock/clock_html/tim/timing_report.htm
XSLTProcess "clock_build.xml"
sch2vhdl -intstyle ise -family xc9500xl -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper clock.ngd
hprep6 -s IEEE1149 -n clock -i clock
taengine -f clock -w --format html1 -l e:\temp\95144\vhdl\clock/clock_html/tim/timing_report.htm
XSLTProcess "clock_build.xml"
sch2vhdl -intstyle ise -family xc9500xl -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -dd _ngo -uc clock.ucf -p xc9500xl clock.ngc clock.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper clock.ngd
hprep6 -s IEEE1149 -n clock -i clock
taengine -f clock -w --format html1 -l e:\temp\95144\vhdl\interface\clock/clock_html/tim/timing_report.htm
XSLTProcess "clock_build.xml"
sch2vhdl -intstyle ise -family spartan3 -flat -suppress -w clock.sch clock.vhf
sch2vhdl -intstyle ise -family spartan3 -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -intstyle ise -dd "e:\cindy\working\ue_extboard\sp3\vhdl\clock/_ngo" -nt timestamp -uc clock.ucf  -p xc3s400-pq208-5 clock.ngc clock.ngd
map -intstyle ise -p xc3s400-pq208-5 -cm area -pr b -k 4 -c 100 -o clock_map.ncd clock.ngd clock.pcf
par -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd clock.pcf
trce -intstyle ise -e 3 -l 3 -s 5 -xml clock clock.ncd -o clock.twr clock.pcf
sch2vhdl -intstyle ise -family spartan3 -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -intstyle ise -dd "e:\cindy\working\ue_extboard\sp3\vhdl\clock/_ngo" -nt timestamp -uc clock.ucf  -p xc3s400-pq208-5 clock.ngc clock.ngd
map -intstyle ise -p xc3s400-pq208-5 -cm area -pr b -k 4 -c 100 -o clock_map.ncd clock.ngd clock.pcf
par -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd clock.pcf
trce -intstyle ise -e 3 -l 3 -s 5 -xml clock clock.ncd -o clock.twr clock.pcf
bitgen -intstyle ise -f clock.ut clock.ncd
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -intstyle ise -dd "e:\cindy\working\ue_extboard\sp3\vhdl\clock/_ngo" -nt timestamp -uc clock.ucf  -p xc3s400-pq208-5 clock.ngc clock.ngd
map -intstyle ise -p xc3s400-pq208-5 -cm area -pr b -k 4 -c 100 -o clock_map.ncd clock.ngd clock.pcf
par -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd clock.pcf
trce -intstyle ise -e 3 -l 3 -s 5 -xml clock clock.ncd -o clock.twr clock.pcf
bitgen -intstyle ise -f clock.ut clock.ncd
ngdbuild -intstyle ise -dd "e:\cindy\working\ue_extboard\sp3\vhdl\clock/_ngo" -nt timestamp -uc clock.ucf  -p xc3s400-pq208-5 clock.ngc clock.ngd
map -intstyle ise -p xc3s400-pq208-5 -cm area -pr b -k 4 -c 100 -o clock_map.ncd clock.ngd clock.pcf
par -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd clock.pcf
trce -intstyle ise -e 3 -l 3 -s 5 -xml clock clock.ncd -o clock.twr clock.pcf
bitgen -intstyle ise -f clock.ut clock.ncd
sch2vhdl -intstyle ise -family spartan3 -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
sch2vhdl -intstyle ise -family spartan3 -flat -suppress -w clock.sch clock.vhf
xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr
ngdbuild -intstyle ise -dd "e:\temp\sp3-u\ue basic board\vhdl\clock/_ngo" -uc clock.ucf  -p xc3s400-pq208-5 clock.ngc clock.ngd
map -intstyle ise -p xc3s400-pq208-5 -cm area -pr b -k 4 -c 100 -o clock_map.ncd clock.ngd clock.pcf
par -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd clock.pcf
trce -intstyle ise -e 3 -l 3 -s 5 -xml clock clock.ncd -o clock.twr clock.pcf
bitgen -intstyle ise -f clock.ut clock.ncd