clock.syr

vhdl经典源代码——时钟设计

#      4-bit 4-to-1 multiplexer    : 2
#      4-bit 8-to-1 multiplexer    : 1
# Adders/Subtractors               : 2
#      15-bit adder                : 1
#      26-bit adder                : 1
# Comparators                      : 2
#      15-bit comparator lessequal : 1
#      26-bit comparator lessequal : 1

Cell Usage :
# BELS                             : 292
#      GND                         : 1
#      INV                         : 17
#      LUT1                        : 1
#      LUT1_L                      : 38
#      LUT2                        : 10
#      LUT2_D                      : 1
#      LUT2_L                      : 24
#      LUT3                        : 23
#      LUT3_L                      : 6
#      LUT4                        : 60
#      LUT4_D                      : 4
#      LUT4_L                      : 7
#      MUXCY                       : 50
#      MUXF5                       : 10
#      VCC                         : 1
#      XORCY                       : 39
# FlipFlops/Latches                : 82
#      FDC                         : 60
#      FDCE                        : 11
#      FDE                         : 4
#      FDP                         : 6
#      FDPE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 15
#      IBUF                        : 1
#      OBUF                        : 14
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                     101  out of   3584     2%  
 Number of Slice Flip Flops:            82  out of   7168     1%  
 Number of 4 input LUTs:               174  out of   7168     2%  
 Number of bonded IOBs:                 16  out of    141    11%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_16/carry:Q                    | NONE                   | 9     |
XLXI_3/qout:Q                      | NONE                   | 9     |
XLXI_1/qout:Q                      | NONE                   | 13    |
XLXI_17/carry:Q                    | NONE                   | 8     |
clk                                | BUFGP                  | 43    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.493ns (Maximum Frequency: 105.337MHz)
   Minimum input arrival time before clock: 4.571ns
   Maximum output required time after clock: 7.896ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_16/carry:Q'
  Clock period: 4.787ns (frequency: 208.888MHz)
  Total number of paths / destination ports: 49 / 14
-------------------------------------------------------------------------
Delay:               4.787ns (Levels of Logic = 2)
  Source:            XLXI_17/tem1_1 (FF)
  Destination:       XLXI_17/carry (FF)
  Source Clock:      XLXI_16/carry:Q rising
  Destination Clock: XLXI_16/carry:Q rising

  Data Path: XLXI_17/tem1_1 to XLXI_17/carry
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              6   0.626   1.148  XLXI_17/tem1_1 (XLXI_17/tem1_1)
     LUT4:I0->O            1   0.479   0.851  XLXI_17/_n00051 (XLXI_17/N2)
     LUT2:I1->O            1   0.479   0.681  XLXI_17/_n00052 (XLXI_17/_n0005)
     FDE:CE                    0.524          XLXI_17/carry
    ----------------------------------------
    Total                      4.787ns (2.108ns logic, 2.679ns route)
                                       (44.0% logic, 56.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_3/qout:Q'
  Clock period: 4.787ns (frequency: 208.888MHz)
  Total number of paths / destination ports: 49 / 14
-------------------------------------------------------------------------
Delay:               4.787ns (Levels of Logic = 2)
  Source:            XLXI_16/tem1_1 (FF)
  Destination:       XLXI_16/carry (FF)
  Source Clock:      XLXI_3/qout:Q rising
  Destination Clock: XLXI_3/qout:Q rising

  Data Path: XLXI_16/tem1_1 to XLXI_16/carry
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              6   0.626   1.148  XLXI_16/tem1_1 (XLXI_16/tem1_1)
     LUT4:I0->O            1   0.479   0.851  XLXI_16/_n00051 (XLXI_16/N2)
     LUT2:I1->O            1   0.479   0.681  XLXI_16/_n00052 (XLXI_16/_n0005)
     FDE:CE                    0.524          XLXI_16/carry
    ----------------------------------------
    Total                      4.787ns (2.108ns logic, 2.679ns route)
                                       (44.0% logic, 56.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_1/qout:Q'
  Clock period: 5.044ns (frequency: 198.244MHz)
  Total number of paths / destination ports: 68 / 13
-------------------------------------------------------------------------
Delay:               5.044ns (Levels of Logic = 4)
  Source:            XLXI_6/cnt_1 (FF)
  Destination:       XLXI_6/qout_3 (FF)
  Source Clock:      XLXI_1/qout:Q rising
  Destination Clock: XLXI_1/qout:Q rising

  Data Path: XLXI_6/cnt_1 to XLXI_6/qout_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             23   0.626   1.741  XLXI_6/cnt_1 (XLXI_6/cnt_1)
     LUT3:I0->O            1   0.479   0.000  XLXI_6/_n0000<1>_rn_211_F (N289)
     MUXF5:I0->O           2   0.314   0.915  XLXI_6/_n0000<1>_rn_211 (XLXI_6/MUX_BLOCK__n0000<1>_MUXF53)
     LUT4:I1->O            1   0.479   0.000  XLXI_6/_n0000<2>31111_G (N288)
     MUXF5:I1->O           1   0.314   0.000  XLXI_6/_n0000<2>31111 (XLXI_6/_n0004<3>)
     FDC:D                     0.176          XLXI_6/qout_3
    ----------------------------------------
    Total                      5.044ns (2.388ns logic, 2.656ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_17/carry:Q'
  Clock period: 5.428ns (frequency: 184.218MHz)
  Total number of paths / destination ports: 91 / 12
-------------------------------------------------------------------------
Delay:               5.428ns (Levels of Logic = 3)
  Source:            XLXI_2/tem1_1 (FF)
  Destination:       XLXI_2/tem1_2 (FF)
  Source Clock:      XLXI_17/carry:Q rising
  Destination Clock: XLXI_17/carry:Q rising

  Data Path: XLXI_2/tem1_1 to XLXI_2/tem1_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              6   0.626   1.148  XLXI_2/tem1_1 (XLXI_2/tem1_1)
     LUT4:I0->O            3   0.479   1.066  XLXI_2/_n001010 (CHOICE84)
     LUT2:I0->O            1   0.479   0.976  XLXI_2/_n001023 (XLXI_2/_n0020<2>)
     LUT4:I0->O            1   0.479   0.000  XLXI_2/_n0005<2>1 (XLXI_2/_n0005<2>)
     FDC:D                     0.176          XLXI_2/tem1_2
    ----------------------------------------
    Total                      5.428ns (2.239ns logic, 3.189ns route)
                                       (41.2% logic, 58.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 9.493ns (frequency: 105.337MHz)
  Total number of paths / destination ports: 2122 / 43
-------------------------------------------------------------------------
Delay:               9.493ns (Levels of Logic = 16)
  Source:            XLXI_3/cnt_25 (FF)
  Destination:       XLXI_3/qout (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_3/cnt_25 to XLXI_3/qout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   1.040  XLXI_3/cnt_25 (XLXI_3/cnt_25)
     LUT4:I0->O            1   0.479   0.851  XLXI_3/_n000469 (CHOICE133)
     LUT2:I1->O            3   0.479   0.830  XLXI_3/_n000470 (CHOICE134)
     LUT4:I2->O            9   0.479   1.125  XLXI_3/_n0004115_1 (XLXI_3/_n0004115)
     LUT2_L:I1->LO         1   0.479   0.000  XLXI_3/norlut1 (XLXI_3/N6)
     MUXCY:S->O            1   0.435   0.000  XLXI_3/norcy_rn_0 (XLXI_3/nor_cyo1)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/Andcy_rn_0 (XLXI_3/And_cyo1)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/norcy_rn_1 (XLXI_3/nor_cyo2)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/Andcy_rn_1 (XLXI_3/And_cyo2)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/norcy_rn_2 (XLXI_3/nor_cyo3)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/Andcy_rn_2 (XLXI_3/And_cyo3)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/norcy_rn_3 (XLXI_3/nor_cyo4)
     MUXCY:CI->O           1   0.056   0.000  XLXI_3/Andcy_rn_3 (XLXI_3/And_cyo4)
     MUXCY:CI->O           1   0.264   0.681  XLXI_3/norcy_rn_4 (XLXI_3/_n0005)
     INV:I->O              1   0.479   0.681  XLXI_3/_n00021_INV_0 (XLXI_3/_n0002)
     FDE:D                     0.176          XLXI_3/qout
    ----------------------------------------
    Total                      9.493ns (4.285ns logic, 5.208ns route)
                                       (45.1% logic, 54.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_16/carry:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.571ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       XLXI_17/carry (FF)
  Destination Clock: XLXI_16/carry:Q rising

  Data Path: rst to XLXI_17/carry
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.715   0.842  rst_IBUF (rst_IBUF)
     LUT4:I2->O            1   0.479   0.851  XLXI_17/_n00051 (XLXI_17/N2)
     LUT2:I1->O            1   0.479   0.681  XLXI_17/_n00052 (XLXI_17/_n0005)
     FDE:CE                    0.524          XLXI_17/carry
    ----------------------------------------
    Total                      4.571ns (2.197ns logic, 2.374ns route)
                                       (48.1% logic, 51.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_3/qout:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.571ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       XLXI_16/carry (FF)
  Destination Clock: XLXI_3/qout:Q rising

  Data Path: rst to XLXI_16/carry
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.715   0.842  rst_IBUF (rst_IBUF)
     LUT4:I2->O            1   0.479   0.851  XLXI_16/_n00051 (XLXI_16/N2)
     LUT2:I1->O            1   0.479   0.681  XLXI_16/_n00052 (XLXI_16/_n0005)
     FDE:CE                    0.524          XLXI_16/carry
    ----------------------------------------
    Total                      4.571ns (2.197ns logic, 2.374ns route)
                                       (48.1% logic, 51.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              2.022ns (Levels of Logic = 1)
  Source:            rst (PAD)
  Destination:       XLXI_1/qout (FF)
  Destination Clock: clk rising

  Data Path: rst to XLXI_1/qout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.715   0.783  rst_IBUF (rst_IBUF)
     FDE:CE                    0.524          XLXI_3/qout
    ----------------------------------------
    Total                      2.022ns (1.239ns logic, 0.783ns route)
                                       (61.3% logic, 38.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_1/qout:Q'
  Total number of paths / destination ports: 34 / 13
-------------------------------------------------------------------------
Offset:              7.896ns (Levels of Logic = 2)
  Source:            XLXI_6/qout_2 (FF)
  Destination:       dataout<1> (PAD)
  Source Clock:      XLXI_1/qout:Q rising

  Data Path: XLXI_6/qout_2 to dataout<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.626   1.201  XLXI_6/qout_2 (XLXI_6/qout_2)
     LUT4:I0->O            1   0.479   0.681  XLXI_4/Mrom_qout_inst_lut4_61 (dataout_1_OBUF)
     OBUF:I->O                 4.909          dataout_1_OBUF (dataout<1>)
    ----------------------------------------
    Total                      7.896ns (6.014ns logic, 1.882ns route)
                                       (76.2% logic, 23.8% route)

=========================================================================
CPU : 14.52 / 16.08 s | Elapsed : 15.00 / 16.00 s
 
--> 

Total memory usage is 93256 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    1 (   0 filtered)