clock.syr

vhdl经典源代码——时钟设计

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: clock.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "clock.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "clock"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : clock
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : clock.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen100.vhd" in Library work.
Architecture behave of Entity fen100 is up to date.
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen24.vhd" in Library work.
Architecture behave of Entity fen24 is up to date.
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen1.vhd" in Library work.
Architecture behave of Entity fen1 is up to date.
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/clock/decode47.vhd" in Library work.
Architecture behave of Entity decode47 is up to date.
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/clock/sel.vhd" in Library work.
Architecture behave of Entity sel is up to date.
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen60.vhd" in Library work.
Architecture behave of Entity fen60 is up to date.
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/clock/clock.vhf" in Library work.
Entity <clock> compiled.
Entity <clock> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <behavioral>).
WARNING:Xst:753 - "E:/temp/sp3-U/UE Basic Board/VHDL/clock/clock.vhf" line 102: Unconnected output port 'carry' of component 'fen24'.
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <fen100> (Architecture <behave>).
Entity <fen100> analyzed. Unit <fen100> generated.

Analyzing Entity <fen24> (Architecture <behave>).
WARNING:Xst:819 - "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen24.vhd" line 31: The following signals are missing in the process sensitivity list:
   tem1, tem2.
Entity <fen24> analyzed. Unit <fen24> generated.

Analyzing Entity <fen1> (Architecture <behave>).
Entity <fen1> analyzed. Unit <fen1> generated.

Analyzing Entity <decode47> (Architecture <behave>).
Entity <decode47> analyzed. Unit <decode47> generated.

Analyzing Entity <sel> (Architecture <behave>).
Entity <sel> analyzed. Unit <sel> generated.

Analyzing Entity <fen60> (Architecture <behave>).
WARNING:Xst:819 - "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen60.vhd" line 30: The following signals are missing in the process sensitivity list:
   tem1, tem2.
Entity <fen60> analyzed. Unit <fen60> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fen60>.
    Related source file is "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen60.vhd".
    Found 1-bit register for signal <carry>.
    Found 4-bit up counter for signal <tem1>.
    Found 4-bit up counter for signal <tem2>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <fen60> synthesized.


Synthesizing Unit <sel>.
    Related source file is "E:/temp/sp3-U/UE Basic Board/VHDL/clock/sel.vhd".
    Found 4-bit register for signal <qout>.
    Found 4-bit 8-to-1 multiplexer for signal <$n0004> created at line 53.
    Found 3-bit adder for signal <$n0005> created at line 51.
    Found 3-bit register for signal <cnt>.
    Found 6-bit register for signal <sel>.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   4 Multiplexer(s).
Unit <sel> synthesized.


Synthesizing Unit <decode47>.
    Related source file is "E:/temp/sp3-U/UE Basic Board/VHDL/clock/decode47.vhd".
    Found 16x8-bit ROM for signal <qout>.
    Summary:
	inferred   1 ROM(s).
Unit <decode47> synthesized.


Synthesizing Unit <fen1>.
    Related source file is "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen1.vhd".
    Found 1-bit register for signal <qout>.
    Found 26-bit adder for signal <$n0003> created at line 35.
    Found 26-bit comparator lessequal for signal <$n0005>.
    Found 26-bit register for signal <cnt>.
    Summary:
	inferred  27 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <fen1> synthesized.


Synthesizing Unit <fen24>.
    Related source file is "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen24.vhd".
    Found 1-bit register for signal <carry>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 4-bit adder for signal <$n0008> created at line 51.
    Found 4-bit adder for signal <$n0009> created at line 48.
    Found 4-bit register for signal <tem1>.
    Found 4-bit register for signal <tem2>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   8 Multiplexer(s).
Unit <fen24> synthesized.


Synthesizing Unit <fen100>.
    Related source file is "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen100.vhd".
    Found 1-bit register for signal <qout>.
    Found 15-bit adder for signal <$n0003> created at line 36.
    Found 15-bit comparator lessequal for signal <$n0005>.
    Found 15-bit register for signal <cnt>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <fen100> synthesized.


Synthesizing Unit <clock>.
    Related source file is "E:/temp/sp3-U/UE Basic Board/VHDL/clock/clock.vhf".
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 5
 15-bit adder                      : 1
 26-bit adder                      : 1
 3-bit adder                       : 1
 4-bit adder                       : 2
# Counters                         : 4
 4-bit up counter                  : 4
# Registers                        : 12
 1-bit register                    : 5
 15-bit register                   : 1
 26-bit register                   : 1
 3-bit register                    : 1
 4-bit register                    : 3
 6-bit register                    : 1
# Comparators                      : 2
 15-bit comparator lessequal       : 1
 26-bit comparator lessequal       : 1
# Multiplexers                     : 3
 4-bit 4-to-1 multiplexer          : 2
 4-bit 8-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <carry> is unconnected in block <XLXI_2>.

Optimizing unit <clock> ...

Optimizing unit <fen60> ...

Optimizing unit <sel> ...

Optimizing unit <fen24> ...

Optimizing unit <fen100> ...

Optimizing unit <fen1> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <XLXI_2/carry> is unconnected in block <clock>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clock, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : clock.ngr
Top Level Output File Name         : clock
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 16

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 25
#      1-bit register              : 17
#      15-bit register             : 1
#      26-bit register             : 1
#      3-bit register              : 1
#      4-bit register              : 5
# Multiplexers                     : 3