clock.vhf

vhdl经典源代码——时钟设计

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : sch2vhdl
--  /   /         Filename : clock.vhf
-- /___/   /\     Timestamp : 03/17/2006 10:22:58
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: D:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w clock.sch clock.vhf
--Design Name: clock
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity clock is
   port ( clk     : in    std_logic; 
          rst     : in    std_logic; 
          dataout : out   std_logic_vector (0 to 7); 
          en      : out   std_logic_vector (5 downto 0));
end clock;

architecture BEHAVIORAL of clock is
   signal XLXN_6  : std_logic;
   signal XLXN_7  : std_logic;
   signal XLXN_9  : std_logic;
   signal XLXN_10 : std_logic;
   signal XLXN_13 : std_logic_vector (3 downto 0);
   signal XLXN_19 : std_logic_vector (3 downto 0);
   signal XLXN_20 : std_logic_vector (3 downto 0);
   signal XLXN_22 : std_logic_vector (3 downto 0);
   signal XLXN_24 : std_logic_vector (3 downto 0);
   signal XLXN_26 : std_logic_vector (3 downto 0);
   signal XLXN_29 : std_logic_vector (3 downto 0);
   component fen100
      port ( clk  : in    std_logic; 
             rst  : in    std_logic; 
             qout : out   std_logic);
   end component;
   
   component fen24
      port ( clk   : in    std_logic; 
             rst   : in    std_logic; 
             carry : out   std_logic; 
             qout1 : out   std_logic_vector (3 downto 0); 
             qout2 : out   std_logic_vector (3 downto 0));
   end component;
   
   component fen1
      port ( clk  : in    std_logic; 
             rst  : in    std_logic; 
             qout : out   std_logic);
   end component;
   
   component decode47
      port ( qin  : in    std_logic_vector (3 downto 0); 
             qout : out   std_logic_vector (7 downto 0));
   end component;
   
   component sel
      port ( clk  : in    std_logic; 
             rst  : in    std_logic; 
             qin1 : in    std_logic_vector (3 downto 0); 
             qin2 : in    std_logic_vector (3 downto 0); 
             qin3 : in    std_logic_vector (3 downto 0); 
             qin4 : in    std_logic_vector (3 downto 0); 
             qin5 : in    std_logic_vector (3 downto 0); 
             qin6 : in    std_logic_vector (3 downto 0); 
             qout : out   std_logic_vector (3 downto 0); 
             nsel : out   std_logic_vector (5 downto 0));
   end component;
   
   component fen60
      port ( clk   : in    std_logic; 
             rst   : in    std_logic; 
             carry : out   std_logic; 
             qout1 : out   std_logic_vector (3 downto 0); 
             qout2 : out   std_logic_vector (3 downto 0));
   end component;
   
begin
   XLXI_1 : fen100
      port map (clk=>clk,
                rst=>rst,
                qout=>XLXN_10);
   
   XLXI_2 : fen24
      port map (clk=>XLXN_7,
                rst=>rst,
                carry=>open,
                qout1(3 downto 0)=>XLXN_19(3 downto 0),
                qout2(3 downto 0)=>XLXN_20(3 downto 0));
   
   XLXI_3 : fen1
      port map (clk=>clk,
                rst=>rst,
                qout=>XLXN_9);
   
   XLXI_4 : decode47
      port map (qin(3 downto 0)=>XLXN_13(3 downto 0),
                qout(7 downto 0)=>dataout(0 to 7));
   
   XLXI_6 : sel
      port map (clk=>XLXN_10,
                qin1(3 downto 0)=>XLXN_24(3 downto 0),
                qin2(3 downto 0)=>XLXN_22(3 downto 0),
                qin3(3 downto 0)=>XLXN_26(3 downto 0),
                qin4(3 downto 0)=>XLXN_29(3 downto 0),
                qin5(3 downto 0)=>XLXN_19(3 downto 0),
                qin6(3 downto 0)=>XLXN_20(3 downto 0),
                rst=>rst,
                nsel(5 downto 0)=>en(5 downto 0),
                qout(3 downto 0)=>XLXN_13(3 downto 0));
   
   XLXI_16 : fen60
      port map (clk=>XLXN_9,
                rst=>rst,
                carry=>XLXN_6,
                qout1(3 downto 0)=>XLXN_24(3 downto 0),
                qout2(3 downto 0)=>XLXN_22(3 downto 0));
   
   XLXI_17 : fen60
      port map (clk=>XLXN_6,
                rst=>rst,
                carry=>XLXN_7,
                qout1(3 downto 0)=>XLXN_26(3 downto 0),
                qout2(3 downto 0)=>XLXN_29(3 downto 0));
   
end BEHAVIORAL;