hdllib.ref

vhdl经典源代码——时钟设计

EN decode47 NULL "E:/temp/sp3-U/UE Basic Board/VHDL/clock/decode47.vhd" sub00/vhpl06 1142562191
EN clock NULL "E:/temp/sp3-U/UE Basic Board/VHDL/clock/clock.vhf" sub00/vhpl12 1142562197
EN sel NULL "E:/temp/sp3-U/UE Basic Board/VHDL/clock/sel.vhd" sub00/vhpl08 1142562193
EN fen1 NULL "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen1.vhd" sub00/vhpl04 1142562189
AR fen60 behave "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen60.vhd" sub00/vhpl11 1142562196
AR fen100 behave "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen100.vhd" sub00/vhpl01 1142562186
AR decode47 behave "E:/temp/sp3-U/UE Basic Board/VHDL/clock/decode47.vhd" sub00/vhpl07 1142562192
AR clock behavioral "E:/temp/sp3-U/UE Basic Board/VHDL/clock/clock.vhf" sub00/vhpl13 1142562198
EN fen24 NULL "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen24.vhd" sub00/vhpl02 1142562187
AR fen24 behave "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen24.vhd" sub00/vhpl03 1142562188
EN fen60 NULL "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen60.vhd" sub00/vhpl10 1142562195
EN fen100 NULL "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen100.vhd" sub00/vhpl00 1142562185
AR fen1 behave "E:/temp/sp3-U/UE Basic Board/VHDL/clock/fen1.vhd" sub00/vhpl05 1142562190
AR sel behave "E:/temp/sp3-U/UE Basic Board/VHDL/clock/sel.vhd" sub00/vhpl09 1142562194