clock.twr

vhdl经典源代码——时钟设计

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\temp\sp3-u\ue basic board\vhdl\clock\clock.ise -intstyle ise -e 3 -l 3 -s 5
-xml clock clock.ncd -o clock.twr clock.pcf


Design file:              clock.ncd
Physical constraint file: clock.pcf
Device,speed:             xc3s400,-5 (ADVANCED 1.35 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
rst         |    4.154(R)|   -1.300(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.723|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Fri Mar 17 10:23:59 2006
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Peak Memory Usage: 82 MB