ps2.twr

vhdl经典源代码——ps2接口设计

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\cindy\working\ue_extboard\sp3\vhdl\ps2\PS2.ise -intstyle ise -e 3 -l 3 -s 4
-xml ps2 ps2.ncd -o ps2.twr ps2.pcf


Design file:              ps2.ncd
Physical constraint file: ps2.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.37 2005-07-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock kb_clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
kb_data     |    0.078(F)|    3.145(F)|kb_clk_BUFGP      |   0.000|
------------+------------+------------+------------------+--------+

Clock kb_clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dataout<0>  |   19.548(R)|kb_clk_BUFGP      |   0.000|
dataout<1>  |   18.349(R)|kb_clk_BUFGP      |   0.000|
dataout<2>  |   20.708(R)|kb_clk_BUFGP      |   0.000|
dataout<3>  |   18.995(R)|kb_clk_BUFGP      |   0.000|
dataout<4>  |   18.809(R)|kb_clk_BUFGP      |   0.000|
dataout<5>  |   20.430(R)|kb_clk_BUFGP      |   0.000|
dataout<6>  |   18.931(R)|kb_clk_BUFGP      |   0.000|
led<0>      |   14.507(R)|kb_clk_BUFGP      |   0.000|
led<1>      |   14.923(R)|kb_clk_BUFGP      |   0.000|
led<2>      |   14.904(R)|kb_clk_BUFGP      |   0.000|
led<3>      |   14.622(R)|kb_clk_BUFGP      |   0.000|
led<4>      |   14.621(R)|kb_clk_BUFGP      |   0.000|
led<5>      |   14.758(R)|kb_clk_BUFGP      |   0.000|
led<6>      |   13.739(R)|kb_clk_BUFGP      |   0.000|
led<7>      |   14.530(R)|kb_clk_BUFGP      |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock kb_clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
kb_clk         |         |    3.480|    2.990|         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Feb 22 15:08:15 2006
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Peak Memory Usage: 82 MB