vga.twr

vhdl经典源代码——vga控制

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\cindy\working\ue_extboard\sp3\vhdl\vga\vga.ise -intstyle ise -e 3 -l 3 -s 5
-xml vga vga.ncd -o vga.twr vga.pcf


Design file:              vga.ncd
Physical constraint file: vga.pcf
Device,speed:             xc3s400,-5 (PRODUCTION 1.37 2005-07-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock orient to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
b           |   12.809(F)|orient_BUFGP      |   0.000|
g           |   14.327(F)|orient_BUFGP      |   0.000|
r           |   13.318(F)|orient_BUFGP      |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    2.758|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock orient
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
orient         |         |         |         |    3.057|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
orient         |b              |   11.549|
orient         |g              |   13.070|
orient         |r              |   12.292|
---------------+---------------+---------+

Analysis completed Wed Feb 22 15:01:56 2006
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Peak Memory Usage: 83 MB