📄 defeqns.htm
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<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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$OpTx$$OpTx$INV$521_INV$825 <= ((NOT ll(5) AND NOT ll(6) AND NOT ll(7) AND NOT ll(8))
<br/> OR (NOT ll(6) AND NOT ll(7) AND NOT ll(4) AND NOT ll(8))
<br/> OR (NOT ll(6) AND NOT ll(7) AND NOT ll(8) AND NOT ll(3))
<br/> OR (NOT ll(6) AND NOT ll(7) AND NOT ll(8) AND NOT ll(2)));
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$OpTx$FX_DC$535 <= ((cc(4) AND cc(3))
<br/> OR (ll(5) AND ll(6) AND ll(7) AND ll(8)));
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$OpTx$FX_DC$542 <= ((NOT cc(4) AND cc(2) AND NOT mmd(0) AND cc(3))
<br/> OR (NOT cc(4) AND NOT cc(2) AND NOT mmd(0) AND NOT cc(3))
<br/> OR (NOT cc(4) AND NOT cc(1) AND NOT mmd(0) AND NOT cc(3))
<br/> OR (NOT cc(2) AND NOT cc(1) AND NOT mmd(0) AND NOT cc(3)));
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$OpTx$FX_DC$543 <= ((ll(7))
<br/> OR (ll(8))
<br/> OR (ll(5) AND ll(6) AND ll(4) AND ll(3)));
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$OpTx$FX_DC$545 <= ((cc(4) AND cc(2))
<br/> OR (cc(4) AND cc(1))
<br/> OR (NOT cc(2) AND cc(3))
<br/> OR (cc(2) AND cc(1) AND NOT cc(3)));
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$OpTx$grbp(3)/grbp(3)_D2_INV$826 <= ((EXP20_.EXP)
<br/> OR (EXP21_.EXP)
<br/> OR (cc(4) AND ll(8))
<br/> OR (mmd(1) AND mmd(0))
<br/> OR (ll(8) AND mmd(0))
<br/> OR (cc(4) AND NOT mmd(1) AND NOT mmd(0))
<br/> OR (cc(2) AND ll(8) AND cc(3)));
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Mcompar__n0036_N3/Mcompar__n0036_N3_D2 <= ((ll(7) AND ll(8))
<br/> OR (ll(5) AND ll(6) AND ll(4) AND ll(8))
<br/> OR (ll(5) AND ll(6) AND ll(8) AND ll(3)));
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_n0033/_n0033_D2 <= ((NOT ll(7) AND NOT ll(8))
<br/> OR (NOT ll(5) AND NOT ll(6) AND NOT ll(8))
<br/> OR (NOT ll(6) AND NOT ll(4) AND NOT ll(8))
<br/> OR (NOT ll(6) AND NOT ll(8) AND NOT ll(3) AND NOT ll(2)));
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b <= b_BUFR;
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b_BUFR <= ((EXP13_.EXP)
<br/> OR (EXP14_.EXP)
<br/> OR (orient AND mmd(1) AND mmd(0) AND NOT $OpTx$FX_DC$535)
<br/> OR (orient AND mmd(1) AND $OpTx$$OpTx$INV$521_INV$825 AND
<br/> grbx(1)/grbx(1)_D2 AND NOT $OpTx$FX_DC$535)
<br/> OR (orient AND NOT mmd(1) AND NOT mmd(0) AND NOT grbx(1)/grbx(1)_D2 AND
<br/> NOT $OpTx$FX_DC$535)
<br/> OR (NOT orient AND NOT mmd(1) AND mmd(0) AND
<br/> $OpTx$$OpTx$INV$521_INV$825 AND NOT $OpTx$FX_DC$535)
<br/> OR (NOT orient AND NOT mmd(1) AND NOT mmd(0) AND grbx(1)/grbx(1)_D2 AND
<br/> NOT $OpTx$FX_DC$535));
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FTCPE_cc0: FTCPE port map (cc(0),'1',fs(2),'0','0');
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FTCPE_cc1: FTCPE port map (cc(1),cc(0),fs(2),'0','0');
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FTCPE_cc2: FTCPE port map (cc(2),cc_T(2),fs(2),'0','0');
<br/> cc_T(2) <= (cc(1) AND cc(0));
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FTCPE_cc3: FTCPE port map (cc(3),cc_T(3),fs(2),'0','0');
<br/> cc_T(3) <= (cc(2) AND cc(1) AND cc(0));
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FTCPE_cc4: FTCPE port map (cc(4),cc_T(4),fs(2),'0','0');
<br/> cc_T(4) <= (cc(2) AND cc(1) AND cc(3) AND cc(0));
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FTCPE_clk_int0: FTCPE port map (clk_int(0),'1',clk,'0','0');
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FTCPE_clk_int1: FTCPE port map (clk_int(1),clk_int(0),clk,'0','0');
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FTCPE_fs0: FTCPE port map (fs(0),'1',clk_int(1),'0','0');
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FTCPE_fs1: FTCPE port map (fs(1),fs(0),clk_int(1),'0','0');
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FTCPE_fs2: FTCPE port map (fs(2),fs_T(2),clk_int(1),'0','0');
<br/> fs_T(2) <= (fs(0) AND fs(1));
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g <= NOT (((cc(4) AND cc(3))
<br/> OR (orient AND NOT $OpTx$grbp(3)/grbp(3)_D2_INV$826)
<br/> OR (NOT orient AND $OpTx$grbp(3)/grbp(3)_D2_INV$826)
<br/> OR (ll(5) AND ll(6) AND ll(7) AND ll(8))));
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grbx(1)/grbx(1)_D2 <= ((EXP11_.EXP)
<br/> OR ($OpTx$FX_DC$542.EXP)
<br/> OR (NOT cc(4) AND cc(2) AND cc(1) AND NOT cc(3))
<br/> OR (NOT cc(4) AND cc(2) AND NOT cc(1) AND cc(3))
<br/> OR (NOT cc(4) AND cc(2) AND cc(3) AND NOT cc(0))
<br/> OR (NOT cc(4) AND cc(1) AND NOT cc(3) AND NOT cc(0))
<br/> OR (NOT cc(4) AND NOT cc(1) AND cc(3) AND NOT cc(0)));
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grby(1)13/grby(1)13_D2 <= ((NOT ll(8))
<br/> OR (vs_OBUF.EXP)
<br/> OR ($OpTx$$OpTx$INV$521_INV$825.EXP)
<br/> OR (NOT ll(5) AND NOT ll(6))
<br/> OR (NOT ll(6) AND NOT ll(7) AND NOT ll(4) AND NOT ll(3))
<br/> OR (NOT ll(6) AND NOT ll(7) AND NOT ll(4) AND NOT ll(2))
<br/> OR (NOT ll(6) AND NOT ll(4) AND NOT ll(3) AND NOT ll(2)));
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grby(3)/grby(3)_D2 <= ((ll(8))
<br/> OR (ll(5) AND ll(6) AND ll(7) AND ll(4)));
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hs <= NOT ((cc(4) AND cc(3)));
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FTCPE_ll0: FTCPE port map (ll(0),'1',NOT cc(4),'0','0');
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FTCPE_ll1: FTCPE port map (ll(1),ll_T(1),NOT cc(4),'0','0');
<br/> ll_T(1) <= ((NOT ll(0))
<br/> OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
<br/> NOT ll(2) AND NOT ll(1)));
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FTCPE_ll2: FTCPE port map (ll(2),ll_T(2),NOT cc(4),'0','0');
<br/> ll_T(2) <= (ll(0) AND ll(1));
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FTCPE_ll3: FTCPE port map (ll(3),ll_T(3),NOT cc(4),'0','0');
<br/> ll_T(3) <= (ll(2) AND ll(0) AND ll(1));
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FTCPE_ll4: FTCPE port map (ll(4),ll_T(4),NOT cc(4),'0','0');
<br/> ll_T(4) <= (ll(3) AND ll(2) AND ll(0) AND ll(1));
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FTCPE_ll5: FTCPE port map (ll(5),ll_T(5),NOT cc(4),'0','0');
<br/> ll_T(5) <= ((ll(4) AND ll(3) AND ll(2) AND ll(0) AND ll(1))
<br/> OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
<br/> NOT ll(2) AND ll(0) AND NOT ll(1)));
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FTCPE_ll6: FTCPE port map (ll(6),ll_T(6),NOT cc(4),'0','0');
<br/> ll_T(6) <= ((ll(5) AND ll(4) AND ll(3) AND ll(2) AND ll(0) AND ll(1))
<br/> OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
<br/> NOT ll(2) AND ll(0) AND NOT ll(1)));
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FTCPE_ll7: FTCPE port map (ll(7),ll_T(7),NOT cc(4),'0','0');
<br/> ll_T(7) <= ((ll(5) AND ll(6) AND ll(4) AND ll(3) AND ll(2) AND ll(0) AND
<br/> ll(1))
<br/> OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
<br/> NOT ll(2) AND ll(0) AND NOT ll(1)));
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FTCPE_ll8: FTCPE port map (ll(8),ll_T(8),NOT cc(4),'0','0');
<br/> ll_T(8) <= ((ll(5) AND ll(6) AND ll(7) AND ll(4) AND ll(3) AND ll(2) AND
<br/> ll(0) AND ll(1))
<br/> OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
<br/> NOT ll(2) AND ll(0) AND NOT ll(1)));
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FDCPE_mmd0: FDCPE port map (mmd(0),mmd_D(0),NOT orient,'0','0');
<br/> mmd_D(0) <= (NOT mmd(1) AND NOT mmd(0));
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FDCPE_mmd1: FDCPE port map (mmd(1),mmd_D(1),NOT orient,'0','0');
<br/> mmd_D(1) <= (NOT mmd(1) AND mmd(0));
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r <= NOT (((EXP17_.EXP)
<br/> OR (EXP18_.EXP)
<br/> OR (cc(4) AND cc(3))
<br/> OR (orient AND NOT mmd(1) AND $OpTx$FX_DC$542)
<br/> OR (orient AND NOT mmd(1) AND mmd(0) AND NOT $OpTx$FX_DC$543)
<br/> OR (orient AND NOT mmd(1) AND mmd(0) AND
<br/> $OpTx$$OpTx$INV$521_INV$825)
<br/> OR (NOT orient AND mmd(1) AND mmd(0) AND NOT $OpTx$FX_DC$543)));
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vs <= NOT ((ll(5) AND ll(6) AND ll(7) AND ll(8)));
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Register Legend:
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
<br/> LDCP (Q,D,G,CLR,PRE);
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