vga.par

vhdl经典源代码——vga控制

Release 7.1.04i par H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

CINDY::  Wed Feb 22 15:01:46 2006

par -w -intstyle ise -ol std -t 1 vga_map.ncd vga.ncd vga.pcf 


Constraints file: vga.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "vga" is an NCD, version 3.1, device xc3s400, package pq208, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.37 2005-07-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of External IOBs             7 out of 141     4%
      Number of LOCed IOBs             7 out of 7     100%

   Number of Slices                   28 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989703) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2
......
......................


Phase 3.2 (Checksum:98b488) REAL time: 3 secs 

Phase 4.8
.
Phase 4.8 (Checksum:98d81f) REAL time: 3 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file vga.ncd


Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 175 unrouted;       REAL time: 3 secs 

Phase 2: 155 unrouted;       REAL time: 4 secs 

Phase 3: 60 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

WARNING:Route - CLK Net:clk_int<1>
may have excessive skew because 1 NON-CLK pins
failed to route using a CLK template.
WARNING:Route - CLK Net:orient_BUFGP
may have excessive skew because 3 NON-CLK pins
failed to route using a CLK template.
WARNING:Route - CLK Net:fs<2>
may have excessive skew because 1 NON-CLK pins
failed to route using a CLK template.
WARNING:Route - CLK Net:cc<4>
may have excessive skew because 9 NON-CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|        orient_BUFGP |      BUFGMUX2| No   |    4 |  0.000     |  0.901      |
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX1| No   |    2 |  0.000     |  0.901      |
+---------------------+--------------+------+------+------------+-------------+
|               cc<4> |         Local|      |   14 |  0.007     |  2.688      |
+---------------------+--------------+------+------+------------+-------------+
|          clk_int<1> |         Local|      |    3 |  0.000     |  2.527      |
+---------------------+--------------+------+------+------------+-------------+
|               fs<2> |         Local|      |    5 |  0.004     |  2.570      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  77 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file vga.ncd



PAR done!